diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2022-01-05 19:23:07 +0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-07 15:28:32 +0000 |
| commit | 08351d27273c15953018395b2eb3fb297a5103b1 (patch) | |
| tree | 18fde7f61e63bb4acb0973510e99b06a94e32940 | |
| parent | 060e89f347a4799edcf51bbd2147d39e2f601d19 (diff) | |
mb/google/brya/var/anahera: Fine tune I2C frequency
Fine tune i2c frequency.
I2C0 - 399.6 kHz
I2C1 - 391.4 kHz
I2C3 - 398.1 kHz
I2C5 - 399.9 kHz
BUG=b:213295817
TEST=build
Change-Id: I9a89820a8d9ae4c9b4ee499e8467426e0670656d
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/anahera/overridetree.cb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 2af5520426..f2d863a8fd 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -47,6 +47,12 @@ chip soc/intel/alderlake #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, .i2c[1] = { .early_init = 1, .speed = I2C_SPEED_FAST, @@ -60,6 +66,12 @@ chip soc/intel/alderlake .fall_time_ns = 400, .data_hold_time_ns = 50, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, }" register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card |