vc/intel/fsp/fsp2_0/graniterapids: Update FSP headers

FSP n-1 headers in vc/intel/fsp/fsp2_0/graniterapid are updated to
pass compilation with full platform codes.

Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

12 files changed, 304 insertions, 9 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h
index 7338538e13..6d5ba0a37b 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h
@@ -31,4 +31,10 @@ are permitted provided that the following conditions are met:
 #ifndef _FSP_ACPI_HOBS_H_
 #define _FSP_ACPI_HOBS_H_
 
+//Typecast HOB pointer to ACPI CXL CEDT table structure
+#define FSP_CXL_CEDT_ACPI_HOB_GUID        { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } }
+
+//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA;
+#define RAS_ACPI_PARAM_HOB_GUID           {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } }
+
 #endif //#ifndef _FSP_ACPI_HOBS_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h
new file mode 100644
index 0000000000..af0dc5055e
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h
@@ -0,0 +1,69 @@
+/** @file
+
+Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+**/
+
+#ifndef __FSP_EDPC_PARAM__
+#define __FSP_EDPC_PARAM__
+
+#pragma pack(1)
+typedef struct {
+  UINT8         Segment;
+  UINT8         Bus;
+  UINT8         Device;
+  UINT8         Function;
+} EDPC_DEV_INFO;
+
+typedef struct {
+  //
+  // There are three possible statuses of Valid infomation
+  // EPDC_INFO_VALID, EDPC_INFO_NOTIFIED, EDPC_INFO_CLEARED
+  //
+  UINT8           Valid;
+  EDPC_DEV_INFO   EdpcTrigger;
+  EDPC_DEV_INFO   EdpcRootPort;
+  UINT8           NotifyType;
+} EDPC_INFO;
+
+typedef struct {
+  UINT16          OsNativeAerSupport;
+  UINT16          Reserved;
+  UINT64          Reserved1[400];
+  EDPC_INFO       EdpcInfo;
+  UINT64          EmcaL1DirAddr;
+  UINT8           EmcaEn;
+  UINT8           ElogEn;
+  UINT8           WheaEnabled;
+  UINT8           WheaSupportEn;
+  UINT64          ReadAckAddress;
+  UINT64          OobReadAckAddress;
+  UINT32          SoftwareSmi;
+} RAS_ACPI_PARAM;
+
+#pragma pack()
+#endif  // __FSP_EDPC_PARAM__
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h
index 93ca55839f..77133a737a 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h
@@ -41,6 +41,40 @@ are permitted provided that the following conditions are met:
 
 typedef struct {
 
+	/**  WHEA Support
+  Enable/Disable WHEA support.
+  0:Disable, 1:Enable
+**/
+  UINT8                       WheaSupportEn;
+
+/**  Enable/Disable WHEA Error Injection Support.
+  0:Disabled, 1:Enabled
+**/
+  UINT8                       WheaErrorInjSupportEn;
+
+/**  Whea EINJ ACPI 5.0 support for set error type with address and vendor extensions.
+  0:Disabled, 1:Enabled
+**/
+  UINT8                       WheaACPI50ErrInjEn;
+
+/**  Whea PCIE Error Injection Support
+  Enable/Disable Whea PCIE Error Injection Support in FSP.
+  0:Disable, 1:Enable
+**/
+  UINT8                       WheaPcieErrInjEn;
+
+/**  Whea PCIe Error Injection Action Table
+  Use Action Table for Whea PCIe Error Injection in FSP.
+  0:Disable, 1:Enable
+**/
+  UINT8                       PcieErrInjActionTable;
+
+/**  IIO eDPC Support
+  Enable/Disable IIO eDPC Support.
+  0:Disabled, 1:On Fatal Error, 2:On Fatal and Non-Fatal Errors
+**/
+  UINT8                       EdpcEn;
+
 /** N/A
 **/
   UINT8                       ReservedSiliconInitUpd[16];
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h
index 65c2a42ff9..f71bc04561 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h
@@ -47,12 +47,28 @@ are permitted provided that the following conditions are met:
 #define MAX_IOU_PER_SOCKET         7
 #endif
 
+#ifndef MAX_IIO_PORTS_PER_STACK
+#define MAX_IIO_PORTS_PER_STACK    1
+#endif
+
+
+#define MAX_IIO_PCIE_PER_SOCKET      1
+
 #define MAX_VMD_STACKS_PER_SOCKET          8  // Max number of stacks per socket supported by VMD
 
 #pragma pack(1)
 
 typedef enum {
   PE0 = 0,
+  PE1,
+  PE2,
+  PE3,
+  PE4,
+  PE5,
+  PEa,
+  PEb,
+  PEc,
+  PEd,
   PE_MAX,
   PE_ = 0xFF   // temporary unknown value
 } IIO_PACKAGE_PE;
@@ -112,15 +128,27 @@ typedef struct {
 } IIO_SLOT_CFG;
 
 typedef struct {
+  UINT8    Address;     // SMBUS address of IO expander which provides NPEM
+  UINT8    Bank;        // Port or bank on IoExpander which provides NPEM
+  UINT8    MuxAddress;  // SMBUS address of MUX used to access NPEM
+  UINT8    MuxChannel;  // Channel of the MUX used to access NPEM
+} IIO_NPEM_CFG;
+
+typedef struct {
 
   IIO_VPP_CFG             Vpp;
+  IIO_NPEM_CFG            Npem;
   IIO_SLOT_CFG            Slot;
 
   UINT8                   VppEnabled      :1;
   UINT8                   VppExpType      :1;
+  UINT8                   NpemSupported   :1;
 
   UINT8                   SlotImplemented :1;
-  UINT8                   Reserved        :4;
+  UINT8                   Retimer1Present :1;
+  UINT8                   Retimer2Present :1;
+  UINT8                   CommonClock     :1;
+  UINT8                   SRIS            :1;
 
   UINT16                  HotPlug             :  1;  // If hotplug is supported on slot connected to this port
   UINT16                  MrlSensorPresent    :  1;  // If MRL is present on slot connected to this port
@@ -212,6 +240,9 @@ typedef struct {
 #define IIO_BIFURCATE_x2x2x2x2x2x2x2x2  0x19
 #define IIO_BIFURCATE_AUTO              0xFF
 
+#define C1_UID                              2
+#define C2_UID                              3
+
 typedef enum {
   IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx,
   IioBifurcation_x4x4x4x4 = IIO_BIFURCATE_x4x4x4x4,
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h
index 1689a4261b..6b4fa356d8 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h
@@ -74,9 +74,6 @@ are permitted provided that the following conditions are met:
 #define MAX_IIO_PORTS_PER_STACK   8
 #endif
 
-#ifndef MAX_IIO_PCIE_PER_SOCKET
-#define MAX_IIO_PCIE_PER_SOCKET   1
-#endif
 
 #ifndef MAX_IIO_PCIROOTS_PER_STACK
 #define MAX_IIO_PCIROOTS_PER_STACK  1
@@ -217,6 +214,7 @@ typedef struct {
   UINT64                  Mmio64Limit;           // Limit of high MMIO configured for this stack in memory map
   UDS_PCIROOT_RES         PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
   UINT64                  VtbarAddress;          // VT-d Base Address
+  UINT64                  ChbcrBarAddress;
 } UDS_STACK_RES;
 
 typedef struct {
@@ -261,6 +259,14 @@ typedef struct {
     UINT64                  PlatGlobalMmio64Limit;  // Global Mmioh Limit [43:0]
     QPI_CPU_DATA            CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
     QPI_IIO_DATA            IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
+    UINT16                  SystemIoBase;           // System IO Base
+    UINT16                  SystemIoLimit;          // System IO Limit
+    UINT32                  SystemMmio32Base;       // System low MMIO base
+    UINT32                  SystemMmio32Limit;
+    UINT32                  Mmio32Granularity;
+    UINT64                  SystemMmio64Base;       // System high MMIO Base
+    UINT64                  SystemMmio64Limit;      // System high MMIO Limit
+    UINT64                  Mmio64Granularity;
     UINT32                  MemTsegSize;
     UINT64                  PciExpressBase;
     UINT32                  PciExpressSize;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h
index ce47106fe0..ad3eec3b3d 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h
@@ -235,6 +235,8 @@ typedef enum {
   MemTypeCxlExpPersistentMem,
   MemTypeCxl2lmDdrCacheMem,
   MemTypeCxlHetero,
+  MemTypeCxlAccVolatileMemHdmDb,
+  MemTypeCxlExpVolatileMemDcd,
   MemTypeMax
 } MEM_TYPE;
 
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h
index 7338538e13..6d5ba0a37b 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h
@@ -31,4 +31,10 @@ are permitted provided that the following conditions are met:
 #ifndef _FSP_ACPI_HOBS_H_
 #define _FSP_ACPI_HOBS_H_
 
+//Typecast HOB pointer to ACPI CXL CEDT table structure
+#define FSP_CXL_CEDT_ACPI_HOB_GUID        { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } }
+
+//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA;
+#define RAS_ACPI_PARAM_HOB_GUID           {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } }
+
 #endif //#ifndef _FSP_ACPI_HOBS_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h
new file mode 100644
index 0000000000..af0dc5055e
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h
@@ -0,0 +1,69 @@
+/** @file
+
+Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+**/
+
+#ifndef __FSP_EDPC_PARAM__
+#define __FSP_EDPC_PARAM__
+
+#pragma pack(1)
+typedef struct {
+  UINT8         Segment;
+  UINT8         Bus;
+  UINT8         Device;
+  UINT8         Function;
+} EDPC_DEV_INFO;
+
+typedef struct {
+  //
+  // There are three possible statuses of Valid infomation
+  // EPDC_INFO_VALID, EDPC_INFO_NOTIFIED, EDPC_INFO_CLEARED
+  //
+  UINT8           Valid;
+  EDPC_DEV_INFO   EdpcTrigger;
+  EDPC_DEV_INFO   EdpcRootPort;
+  UINT8           NotifyType;
+} EDPC_INFO;
+
+typedef struct {
+  UINT16          OsNativeAerSupport;
+  UINT16          Reserved;
+  UINT64          Reserved1[400];
+  EDPC_INFO       EdpcInfo;
+  UINT64          EmcaL1DirAddr;
+  UINT8           EmcaEn;
+  UINT8           ElogEn;
+  UINT8           WheaEnabled;
+  UINT8           WheaSupportEn;
+  UINT64          ReadAckAddress;
+  UINT64          OobReadAckAddress;
+  UINT32          SoftwareSmi;
+} RAS_ACPI_PARAM;
+
+#pragma pack()
+#endif  // __FSP_EDPC_PARAM__
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h
index 93ca55839f..5aa10ee72e 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h
@@ -41,6 +41,40 @@ are permitted provided that the following conditions are met:
 
 typedef struct {
 
+/**  WHEA Support
+  Enable/Disable WHEA support.
+  0:Disable, 1:Enable
+**/
+  UINT8                       WheaSupportEn;
+
+/**  Enable/Disable WHEA Error Injection Support.
+  0:Disabled, 1:Enabled
+**/
+  UINT8                       WheaErrorInjSupportEn;
+
+/**  Whea EINJ ACPI 5.0 support for set error type with address and vendor extensions.
+  0:Disabled, 1:Enabled
+**/
+  UINT8                       WheaACPI50ErrInjEn;
+
+/**  Whea PCIE Error Injection Support
+  Enable/Disable Whea PCIE Error Injection Support in FSP.
+  0:Disable, 1:Enable
+**/
+  UINT8                       WheaPcieErrInjEn;
+
+/**  Whea PCIe Error Injection Action Table
+  Use Action Table for Whea PCIe Error Injection in FSP.
+  0:Disable, 1:Enable
+**/
+  UINT8                       PcieErrInjActionTable;
+
+/**  IIO eDPC Support
+  Enable/Disable IIO eDPC Support.
+  0:Disabled, 1:On Fatal Error, 2:On Fatal and Non-Fatal Errors
+**/
+  UINT8                       EdpcEn;
+
 /** N/A
 **/
   UINT8                       ReservedSiliconInitUpd[16];
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h
index 65c2a42ff9..53dd0ea75b 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h
@@ -47,17 +47,40 @@ are permitted provided that the following conditions are met:
 #define MAX_IOU_PER_SOCKET         7
 #endif
 
+#ifndef MAX_IIO_PORTS_PER_STACK
+#define MAX_IIO_PORTS_PER_STACK    1
+#endif
+
+
+#define MAX_IIO_PCIE_PER_SOCKET      1
+
 #define MAX_VMD_STACKS_PER_SOCKET          8  // Max number of stacks per socket supported by VMD
 
 #pragma pack(1)
 
 typedef enum {
   PE0 = 0,
+  PE1,
+  PE2,
+  PE3,
+  PE4,
+  PE5,
+  PEa,
+  PEb,
+  PEc,
+  PEd,
   PE_MAX,
   PE_ = 0xFF   // temporary unknown value
 } IIO_PACKAGE_PE;
 
 typedef struct {
+  UINT8    Address;     // SMBUS address of IO expander which provides NPEM
+  UINT8    Bank;        // Port or bank on IoExpander which provides NPEM
+  UINT8    MuxAddress;  // SMBUS address of MUX used to access NPEM
+  UINT8    MuxChannel;  // Channel of the MUX used to access NPEM
+} IIO_NPEM_CFG;
+
+typedef struct {
   UINT8    SLOTEIP[MAX_IIO_PORTS_PER_SOCKET];          // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
   UINT8    SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET];        // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
   UINT8    SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET];        // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
@@ -114,13 +137,18 @@ typedef struct {
 typedef struct {
 
   IIO_VPP_CFG             Vpp;
+  IIO_NPEM_CFG            Npem;
   IIO_SLOT_CFG            Slot;
 
   UINT8                   VppEnabled      :1;
   UINT8                   VppExpType      :1;
+  UINT8                   NpemSupported   :1;
 
   UINT8                   SlotImplemented :1;
-  UINT8                   Reserved        :4;
+  UINT8                   Retimer1Present :1;
+  UINT8                   Retimer2Present :1;
+  UINT8                   CommonClock     :1;
+  UINT8                   SRIS            :1;
 
   UINT16                  HotPlug             :  1;  // If hotplug is supported on slot connected to this port
   UINT16                  MrlSensorPresent    :  1;  // If MRL is present on slot connected to this port
@@ -212,6 +240,9 @@ typedef struct {
 #define IIO_BIFURCATE_x2x2x2x2x2x2x2x2  0x19
 #define IIO_BIFURCATE_AUTO              0xFF
 
+#define C1_UID                              2
+#define C2_UID                              3
+
 typedef enum {
   IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx,
   IioBifurcation_x4x4x4x4 = IIO_BIFURCATE_x4x4x4x4,
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h
index 1689a4261b..6631a39452 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h
@@ -74,10 +74,6 @@ are permitted provided that the following conditions are met:
 #define MAX_IIO_PORTS_PER_STACK   8
 #endif
 
-#ifndef MAX_IIO_PCIE_PER_SOCKET
-#define MAX_IIO_PCIE_PER_SOCKET   1
-#endif
-
 #ifndef MAX_IIO_PCIROOTS_PER_STACK
 #define MAX_IIO_PCIROOTS_PER_STACK  1
 #endif
@@ -217,6 +213,7 @@ typedef struct {
   UINT64                  Mmio64Limit;           // Limit of high MMIO configured for this stack in memory map
   UDS_PCIROOT_RES         PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
   UINT64                  VtbarAddress;          // VT-d Base Address
+  UINT64                  ChbcrBarAddress;
 } UDS_STACK_RES;
 
 typedef struct {
@@ -261,6 +258,14 @@ typedef struct {
     UINT64                  PlatGlobalMmio64Limit;  // Global Mmioh Limit [43:0]
     QPI_CPU_DATA            CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
     QPI_IIO_DATA            IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
+    UINT16                  SystemIoBase;           // System IO Base
+    UINT16                  SystemIoLimit;          // System IO Limit
+    UINT32                  SystemMmio32Base;       // System low MMIO base
+    UINT32                  SystemMmio32Limit;
+    UINT32                  Mmio32Granularity;
+    UINT64                  SystemMmio64Base;       // System high MMIO Base
+    UINT64                  SystemMmio64Limit;      // System high MMIO Limit
+    UINT64                  Mmio64Granularity;
     UINT32                  MemTsegSize;
     UINT64                  PciExpressBase;
     UINT32                  PciExpressSize;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h
index ce47106fe0..ad3eec3b3d 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h
@@ -235,6 +235,8 @@ typedef enum {
   MemTypeCxlExpPersistentMem,
   MemTypeCxl2lmDdrCacheMem,
   MemTypeCxlHetero,
+  MemTypeCxlAccVolatileMemHdmDb,
+  MemTypeCxlExpVolatileMemDcd,
   MemTypeMax
 } MEM_TYPE;