diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2017-11-24 23:12:15 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-02 05:24:21 +0000 |
| commit | b0de851ebb032bd1517790b1c07d408d84e82f94 (patch) | |
| tree | d5f87b12cbf1ac5d7998016b284a5dd1f8e53b7a | |
| parent | 3f75f5da42c30ee9e0b6e20abd8c896aa5cd9dcf (diff) | |
arch/riscv: Return from trap_handler instead of jumping out
Change-Id: I8dbed5dbe377d3a02e58a3bc16a1ee112b28bea9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/arch/riscv/trap_handler.c | 9 | ||||
| -rw-r--r-- | src/arch/riscv/trap_util.S | 1 |
2 files changed, 3 insertions, 7 deletions
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 288b05d1d1..aea9b4d88b 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -69,7 +69,6 @@ void handle_supervisor_call(trapframe *tf) { } tf->gpr[10] = returnValue; write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } static const char *const exception_names[] = { @@ -212,16 +211,16 @@ void trap_handler(trapframe *tf) case CAUSE_MISALIGNED_LOAD: print_trap_information(tf); handle_misaligned_load(tf); - break; + return; case CAUSE_MISALIGNED_STORE: print_trap_information(tf); handle_misaligned_store(tf); - break; + return; case CAUSE_SUPERVISOR_ECALL: /* Don't print so we make console putchar calls look the way they should */ handle_supervisor_call(tf); - break; + return; default: printk(BIOS_EMERG, "================================\n"); printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); @@ -264,7 +263,6 @@ void handle_misaligned_load(trapframe *tf) { // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } void handle_misaligned_store(trapframe *tf) { @@ -292,5 +290,4 @@ void handle_misaligned_store(trapframe *tf) { // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 98db85c4cb..3036f069ab 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -141,7 +141,6 @@ trap_entry: move a0,sp jal trap_handler - .global trap_return trap_return: csrr a0, mscratch restore_regs |