nb/intel/gm45: Use PCI bitwise ops

While we are at it, also reflow a few lines that fit in 96 characters.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42189
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 74 insertions, 140 deletions

diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index 44917465d6..17838809fa 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -40,12 +40,12 @@ void gm45_early_reset(void/*const timings_t *const timings*/)
 				CxDRBy_BOUND_MB(r+1, 128);
 	}
 	/* Set DCC mode to no operation and do magic 0xf0 thing. */
-	MCHBAR32(DCC_MCHBAR) =
-		(MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP;
-	u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
-	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 |  (1 << 2));
+	MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP;
+
+	pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
+
+	pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2));
+
 	/* Normally, we would set this after successful raminit. */
 	MCHBAR32(DCC_MCHBAR) |= (1 << 19);
 
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 3d48ca2c2b..c771ea2deb 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -31,8 +31,8 @@ void gtt_write(u32 reg, u32 data)
 
 static u32 get_cdclk(struct device *const dev)
 {
-	const u16 cdclk_sel =
-		pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK;
+	const u16 cdclk_sel = pci_read_config16(dev, GCFGC_OFFSET) & GCFGC_CD_MASK;
+
 	switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) {
 	case VCO_2666:
 	case VCO_4000:
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index 24633cf96e..102af1c4c3 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -19,9 +19,6 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
 	const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0);
 	const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0);
 
-	u16 reg16;
-	u32 reg32;
-
 	printk(BIOS_DEBUG, "Enabling IGD.\n");
 
 	/* HSync/VSync */
@@ -35,15 +32,10 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
 	};
 	const int f0_12 = (pci_read_config16(igd_dev, 0xf0) >> 12) & 1;
 	const int vco = raminit_read_vco_index();
-	reg16 = pci_read_config16(igd_dev, 0xcc);
-	reg16 &= 0xfc00;
-	reg16 |= display_clock_from_f0_and_vco[f0_12][vco];
-	pci_write_config16(igd_dev, 0xcc, reg16);
 
-	reg16 = pci_read_config16(mch_dev, D0F0_GGC);
-	reg16 &= 0xf00f;
-	reg16 |= sysinfo->ggc;
-	pci_write_config16(mch_dev, D0F0_GGC, reg16);
+	pci_update_config16(igd_dev, 0xcc, 0xfc00, display_clock_from_f0_and_vco[f0_12][vco]);
+
+	pci_update_config16(mch_dev, D0F0_GGC, 0xf00f, sysinfo->ggc);
 
 	if ((sysinfo->gfx_type != GMCH_GL40) &&
 			(sysinfo->gfx_type != GMCH_GS40) &&
@@ -54,21 +46,13 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
 			pci_write_config32(mch_dev, D0F0_DEVEN, deven | 2);
 
 		/* Some IGD related settings on D1:F0. */
-		reg16 = pci_read_config16(peg_dev, 0xa08);
-		reg16 &= ~(1 << 15);
-		pci_write_config16(peg_dev, 0xa08, reg16);
+		pci_and_config16(peg_dev, 0xa08, (u16)~(1 << 15));
 
-		reg16 = pci_read_config16(peg_dev, 0xa84);
-		reg16 |= (1 << 8);
-		pci_write_config16(peg_dev, 0xa84, reg16);
+		pci_or_config16(peg_dev, 0xa84, 1 << 8);
 
-		reg16 = pci_read_config16(peg_dev, 0xb00);
-		reg16 |= (3 << 8) | (7 << 3);
-		pci_write_config16(peg_dev, 0xb00, reg16);
+		pci_or_config16(peg_dev, 0xb00, (3 << 8) | (7 << 3));
 
-		reg32 = pci_read_config32(peg_dev, 0xb14);
-		reg32 &= ~(1 << 17);
-		pci_write_config32(peg_dev, 0xb14, reg32);
+		pci_and_config32(peg_dev, 0xb14, ~(1 << 17));
 
 		if (!(deven & 2) || no_peg) {
 			/* Disable PEG finally. */
@@ -76,16 +60,14 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
 					   "PEG in favor of IGD.\n");
 			MCHBAR8(0xc14) |= (1 << 5) | (1 << 0);
 
-			reg32 = pci_read_config32(peg_dev, 0x200);
-			reg32 |= (1 << 18);
-			pci_write_config32(peg_dev, 0x200, reg32);
-			reg16 = pci_read_config16(peg_dev, 0x224);
-			reg16 |= (1 << 8);
-			pci_write_config16(peg_dev, 0x224, reg16);
-			reg32 = pci_read_config32(peg_dev, 0x200);
-			reg32 &= ~(1 << 18);
-			pci_write_config32(peg_dev, 0x200, reg32);
-			while (pci_read_config32(peg_dev, 0x214) & 0x000f0000);
+			pci_or_config32(peg_dev, 0x200, 1 << 18);
+
+			pci_or_config16(peg_dev, 0x224, 1 << 8);
+
+			pci_and_config32(peg_dev, 0x200, ~(1 << 18));
+
+			while (pci_read_config32(peg_dev, 0x214) & (0xf << 16))
+				;
 
 			pci_write_config32(mch_dev, D0F0_DEVEN, deven & ~2);
 			MCHBAR8(0xc14) &= ~((1 << 5) | (1 << 0));
@@ -99,12 +81,9 @@ static void disable_igd(const sysinfo_t *const sysinfo)
 
 	printk(BIOS_DEBUG, "Disabling IGD.\n");
 
-	u16 reg16;
+	/* Disable Graphics Stolen Memory. */
+	pci_update_config16(mch_dev, D0F0_GGC, 0xff0f, 0x0002);
 
-	reg16 = pci_read_config16(mch_dev, D0F0_GGC);
-	reg16 &= 0xff0f; /* Disable Graphics Stolen Memory. */
-	reg16 |= 0x0002; /* Disable IGD. */
-	pci_write_config16(mch_dev, D0F0_GGC, reg16);
 	MCHBAR8(0xf10) |= (1 << 0);
 
 	if (!(pci_read_config8(mch_dev, D0F0_CAPID0 + 4) & (1 << (33 - 32)))) {
@@ -114,9 +93,7 @@ static void disable_igd(const sysinfo_t *const sysinfo)
 	}
 
 	/* Hide IGD. */
-	u32 deven = pci_read_config32(mch_dev, D0F0_DEVEN);
-	deven &= ~(3 << 3);
-	pci_write_config32(mch_dev, D0F0_DEVEN, deven);
+	pci_and_config32(mch_dev, D0F0_DEVEN, ~(3 << 3));
 }
 
 void init_igd(const sysinfo_t *const sysinfo)
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 439127d17d..09df12d18a 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -50,11 +50,10 @@ void init_iommu()
 	if (stepping == STEPPING_B3) {
 		MCHBAR8(0xffc) |= 1 << 4;
 		const pci_devfn_t peg = PCI_DEV(0, 1, 0);
+
 		/* FIXME: proper test? */
-		if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) {
-			int val = pci_read_config32(peg, 0xfc) | (1 << 15);
-			pci_write_config32(peg, 0xfc, val);
-		}
+		if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff)
+			pci_or_config32(peg, 0xfc, 1 << 15);
 	}
 
 	/* final */
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index b3dbe16b75..0308e216c7 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -259,12 +259,12 @@ static void gm45_init(void *const chip_info)
 			break;
 		}
 		for (; fn >= 0; --fn) {
-			const struct device *const d =
-				pcidev_on_root(dev, fn);
-			if (!d || d->enabled) continue;
-			const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
+			const struct device *const d = pcidev_on_root(dev, fn);
+			if (!d || d->enabled)
+				continue;
+			/* FIXME: Using bitwise ops changes the binary */
 			pci_write_config32(d0f0, D0F0_DEVEN,
-					   deven & ~(1 << (bit_base + fn)));
+				pci_read_config32(d0f0, D0F0_DEVEN) & ~(1 << (bit_base + fn)));
 		}
 	}
 
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index e4d11e335c..88c3cee117 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -92,9 +92,6 @@ static void init_pcie(const int peg_enabled,
 		      const int sdvo_enabled,
 		      const int peg_x16)
 {
-	u8 tmp8;
-	u16 tmp16;
-	u32 tmp;
 	const pci_devfn_t mch = PCI_DEV(0, 0, 0);
 	const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
 
@@ -103,20 +100,17 @@ static void init_pcie(const int peg_enabled,
 		sdvo_enabled?"enabled":"disabled");
 
 	if (peg_enabled) {
-		tmp8 = pci_read_config8(mch, D0F0_DEVEN) | (1 << 1);
-		pci_write_config8(mch, D0F0_DEVEN, tmp8);
+		pci_or_config8(mch, D0F0_DEVEN, 1 << 1);
 
-		tmp8 = pci_read_config8(pciex, 0x224) & ~31;
-		pci_write_config8(pciex, 0x224, tmp8 | (peg_x16?16:0) | 1);
+		pci_write_config8(pciex, 0x224,
+			(pci_read_config8(pciex, 0x224) & ~31) | (peg_x16 ? 16 : 0) | 1);
 
-		tmp16 = pci_read_config16(pciex, 0x224) & ~(1 << 8);
-		pci_write_config16(pciex, 0x224, tmp16);
+		pci_and_config16(pciex, 0x224, ~(1 << 8));
 
 		/* FIXME: fill in: slot or fixed? -> devicetree */
 		int peg_is_slot = 0;
 		if (peg_is_slot) {
-			tmp16 = pci_read_config16(pciex, PEG_CAP) | (1 << 8);
-			pci_write_config16(pciex, PEG_CAP, tmp16);
+			pci_or_config16(pciex, PEG_CAP, 1 << 8);
 		}
 
 		/* FIXME: fill in: slot number, slot power -> devicetree */
@@ -125,20 +119,16 @@ static void init_pcie(const int peg_enabled,
 		/* peg_power := val * 10^-exp */
 		int peg_power_val = 75;
 		int peg_power_exp = 0; /* 0..3 */
-		tmp = (peg_slot << 17) | (peg_power_exp << 15) |
-			(peg_power_val << 7);
+		const u32 tmp = (peg_slot << 17) | (peg_power_exp << 15) | (peg_power_val << 7);
 		pci_write_config32(pciex, SLOTCAP, tmp);
 
 		/* GPEs */
-		tmp8 = pci_read_config8(pciex, PEGLC) | 7;
-		pci_write_config8(pciex, PEGLC, tmp8);
+		pci_or_config8(pciex, PEGLC, 7);
 
 		/* VC0: TC0 only, VC0 only */
-		tmp8 = pci_read_config8(pciex, D1F0_VC0RCTL);
-		pci_write_config8(pciex, D1F0_VC0RCTL, tmp8 & 1);
+		pci_and_config8(pciex, D1F0_VC0RCTL, 1);
 
-		tmp8 = pci_read_config8(pciex, D1F0_VCCAP);
-		pci_write_config8(pciex, D1F0_VCCAP, tmp8 & ~7);
+		pci_and_config8(pciex, D1F0_VCCAP, ~7);
 	}
 }
 
@@ -149,37 +139,26 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
 
 	/* Prerequisites for ASPM: */
 	if (peg_enabled) {
-		tmp32 = pci_read_config32(pciex, 0x200) | (3 << 13);
-		pci_write_config32(pciex, 0x200, tmp32);
+		pci_or_config32(pciex, 0x200, 3 << 13);
 
-		tmp32 = pci_read_config32(pciex, 0x0f0);
-		tmp32 &= ~((1 << 27) | (1 << 26));
-		pci_write_config32(pciex, 0x0f0, tmp32);
+		pci_and_config32(pciex, 0x0f0, ~((1 << 27) | (1 << 26)));
 
-		tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24);
-		pci_write_config32(pciex, 0x0f0, tmp32);
+		pci_or_config32(pciex, 0x0f0, 3 << 24);
 
-		tmp32 = pci_read_config32(pciex, 0x0f4) & ~(1 << 4);
-		pci_write_config32(pciex, 0x0f4, tmp32);
+		pci_and_config32(pciex, 0x0f4, ~(1 << 4));
 
-		tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 0);
-		pci_write_config32(pciex, 0x0fc, tmp32);
+		pci_or_config32(pciex, 0x0fc, 1 << 0);
 
-		tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 1);
-		pci_write_config32(pciex, 0x0fc, tmp32);
+		pci_or_config32(pciex, 0x0fc, 1 << 1);
 
-		tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 4);
-		pci_write_config32(pciex, 0x0fc, tmp32);
+		pci_or_config32(pciex, 0x0fc, 1 << 4);
 
-		tmp32 = pci_read_config32(pciex, 0x0fc) & ~(7 << 5);
-		pci_write_config32(pciex, 0x0fc, tmp32);
+		pci_and_config32(pciex, 0x0fc, ~(7 << 5));
 
 		/* Set L0s, L1 supported in LCTL? */
-		tmp32 = pci_read_config32(pciex, 0x0b0) | (3 << 0);
-		pci_write_config32(pciex, 0x0b0, tmp32);
+		pci_or_config32(pciex, 0x0b0, 3 << 0);
 
-		tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24);
-		pci_write_config32(pciex, 0x0f0, tmp32);
+		pci_or_config32(pciex, 0x0f0, 3 << 24);
 
 		tmp32 = pci_read_config32(pciex, 0x0f0);
 		if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1))
@@ -217,38 +196,25 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
 		DMIBAR32(0x0e2c) = 0x88d07333;
 	}
 	if (peg_enabled) {
-		tmp32 = pci_read_config32(pciex, 0xa08) & ~(1 << 15);
-		pci_write_config32(pciex, 0xa08, tmp32);
+		pci_and_config32(pciex, 0xa08, ~(1 << 15));
 
-		tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8);
-		pci_write_config32(pciex, 0xa84, tmp32);
+		pci_or_config32(pciex, 0xa84, 1 << 8);
 
-		tmp32 = pci_read_config32(pciex, 0xb14) & ~(1 << 17);
-		pci_write_config32(pciex, 0xb14, tmp32);
+		pci_and_config32(pciex, 0xb14, ~(1 << 17));
 
-		tmp32 = pci_read_config32(pciex, 0xb00) | (3 << 8);
-		pci_write_config32(pciex, 0xb00, tmp32);
+		pci_or_config32(pciex, 0xb00, 3 << 8);
 
-		tmp32 = pci_read_config32(pciex, 0xb00) | (7 << 3);
-		pci_write_config32(pciex, 0xb00, tmp32);
+		pci_or_config32(pciex, 0xb00, 7 << 3);
 
-		tmp32 = pci_read_config32(pciex, 0xa84) & ~(1 << 8);
-		pci_write_config32(pciex, 0xa84, tmp32);
+		pci_and_config32(pciex, 0xa84, ~(1 << 8));
 
-		tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8);
-		pci_write_config32(pciex, 0xa84, tmp32);
+		pci_or_config32(pciex, 0xa84, 1 << 8);
 
-		tmp32 = pci_read_config32(pciex, 0xb04);
-		tmp32 = (tmp32 & ~(0x1f << 23)) | (0xe << 23);
-		pci_write_config32(pciex, 0xb04, tmp32);
+		pci_update_config32(pciex, 0xb04, ~(0x1f << 23), 0x0e << 23);
 
-		tmp32 = pci_read_config32(pciex, 0xb04);
-		tmp32 |= (1 << 31);
-		pci_write_config32(pciex, 0xb04, tmp32);
+		pci_or_config32(pciex, 0xb04, 1 << 31);
 
-		tmp32 = pci_read_config32(pciex, 0xb04);
-		tmp32 = (tmp32 & ~(0x03 << 29)) | (0x1 << 29);
-		pci_write_config32(pciex, 0xb04, tmp32);
+		pci_update_config32(pciex, 0xb04, ~(0x03 << 29), 0x01 << 29);
 	}
 
 
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 86c7ace983..b95e5631b9 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -808,8 +808,7 @@ static void set_igd_memory_frequencies(const sysinfo_t *const sysinfo)
 	pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc);
 
 	/* Clear update bit. */
-	pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET,
-		pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET) & ~GCFGC_UPDATE);
+	pci_and_config16(GCFGC_PCIDEV, GCFGC_OFFSET, ~GCFGC_UPDATE);
 
 	/* Set display clock select bit. */
 	pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET,
@@ -1229,10 +1228,7 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode
 		}
 		/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
 		   which requires to have TSEG_BASE aligned to TSEG_SIZE. */
-		u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
-		reg8 &= ~0x7;
-		reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
-		pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
+		pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
 		uma_sizem += 2;
 	}
 
@@ -1560,10 +1556,9 @@ static void jedec_init(const timings_t *const timings,
 
 	MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP;
 
-	u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
-	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 |  (1 << 2));
+	pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
+
+	pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2);
 	udelay(2);
 
 				  /* 5  6  7  8  9 10 11 12 */
@@ -1701,7 +1696,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
 	const timings_t *const timings = &sysinfo->selected_timings;
 
 	int ch;
-	u8 reg8;
 
 	timestamp_add_now(TS_BEFORE_INITRAM);
 
@@ -1773,10 +1767,10 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
 
 	/* Announce normal operation, initialization completed. */
 	MCHBAR32(DCC_MCHBAR) |= (0x7 << 16) | (0x1 << 19);
-	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2));
-	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-	pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
+
+	pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2);
+
+	pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
 
 
 	/* Take a breath (the reader). */
@@ -1811,8 +1805,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
 	dram_optimizations(timings, dimms);
 
 	/* Mark raminit being finished. :-) */
-	u8 tmp8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2) & ~(1 << 7);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, tmp8);
+	pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7));
 
 	raminit_thermal(sysinfo);
 	init_igd(sysinfo);
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index d51061267f..22aaee62d8 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -80,9 +80,8 @@ void mainboard_romstage_entry(void)
 
 	mb_post_raminit_setup();
 
-	const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
 	/* Disable D4F0 (unknown signal controller). */
-	pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
+	pci_and_config32(MCH_DEV, D0F0_DEVEN, ~0x4000);
 
 	init_pm(&sysinfo, 0);