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authorSubrata Banik <subratabanik@google.com>2024-07-16 14:07:45 +0000
committerSubrata Banik <subratabanik@google.com>2024-07-19 03:54:44 +0000
commita52e8e7b86e7d324bc4a5995f17f4d5dc4768a75 (patch)
tree85c48bea40ed78a6c335d5a45a7c2cbce33007bb
parent9106a5a346fe6946bcf26b6427f7ace48ed48c44 (diff)
device/pci_ids: Add new Intel PTL device IDs for DID2
This patch adds new DID2 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the graphics driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Iab499070c87e020e36901b4ea453a1893bd16ea0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83491 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/include/device/pci_ids.h4
-rw-r--r--src/soc/intel/common/block/graphics/graphics.c4
2 files changed, 6 insertions, 2 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 2875dff791..3dd3ec9b59 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4192,7 +4192,9 @@
#define PCI_DID_INTEL_LNL_M_GT2 0x64a0
#define PCI_DID_INTEL_TWL_GT1_1 0x46d3
#define PCI_DID_INTEL_TWL_GT1_2 0x46d4
-#define PCI_DID_INTEL_PTL_GT2 0x64a0
+#define PCI_DID_INTEL_PTL_U_GT2_1 0xb090
+#define PCI_DID_INTEL_PTL_H_GT2_1 0xb080
+#define PCI_DID_INTEL_PTL_H_GT2_2 0xb0a0
/* Intel Northbridge Ids */
#define PCI_DID_INTEL_APL_NB 0x5af0
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 1606b96485..f1e7d7e547 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -343,7 +343,9 @@ const struct device_operations graphics_ops = {
};
static const unsigned short pci_device_ids[] = {
- PCI_DID_INTEL_PTL_GT2,
+ PCI_DID_INTEL_PTL_U_GT2_1,
+ PCI_DID_INTEL_PTL_H_GT2_1,
+ PCI_DID_INTEL_PTL_H_GT2_2,
PCI_DID_INTEL_LNL_M_GT2,
PCI_DID_INTEL_RPL_U_GT1,
PCI_DID_INTEL_RPL_U_GT2,