diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-06 19:35:56 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 17:17:09 +0000 |
| commit | 9e00a817f3b195b907ebd94dd408f0c35104d96e (patch) | |
| tree | 434c8eb8028d496c20e4a232b81c81cf4a576985 | |
| parent | 42914feb1f3c6c90201eb3b1753495f93c759690 (diff) | |
soc/intel/xeon_sp: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I22650f539a1646f93f2c6494cbf54b8ca785d6ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pmc.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/pmutil.c | 15 |
3 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index b4d6df987e..63b15cd0de 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -121,4 +121,7 @@ uint16_t get_pmbase(void); void pmc_lock_smi(void); +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + #endif diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index 69299b6057..d49986339c 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -22,6 +22,7 @@ #define PWRMBASE 0x48 #define GEN_PMCON_A 0xa0 #define DISB (1 << 23) +#define MS4V (1 << 18) #define GBL_RST_STS (1 << 16) #define SMI_LOCK (1 << 4) #define GEN_PMCON_B 0xa4 diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index c63285c69b..14c7da83b9 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -179,3 +179,18 @@ void pmc_soc_set_afterg3_en(const bool on) reg8 |= SLEEP_AFTER_POWER_FAIL; pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8); } + +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + const pci_devfn_t dev = PCH_DEV_PMC; + + reg_val = pci_read_config32(dev, GEN_PMCON_A); + /* + * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit + */ + reg_val &= ~(MS4V); + + pci_write_config32(dev, GEN_PMCON_A, reg_val); +} |