soc/amd/picasso: Move BERT region to cbmem

Allocate storage for the BERT reserved memory in cbmem, and add it in
response to a romstage hook.  Add a Kconfig option for adjusting the
size reserved.  This is different from the Stoney Ridge implementation
where it was intentionally oversized to ease MTRR use and to keep TSEG
aligned.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38694
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 38 insertions, 23 deletions

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 842ba0cd37..4759f01ecc 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -199,6 +199,13 @@ config ACPI_BERT
 	  ACPI Boot Error Record Table.  This option reserves an 8MB region
 	  for building the error structures.
 
+config ACPI_BERT_SIZE
+	hex
+	default 0x4000
+	help
+	  Specify the amount of DRAM reserved for gathering the data used to
+	  generate the ACPI table.
+
 config RO_REGION_ONLY
 	string
 	depends on CHROMEOS
diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c
index 2970b942ef..cdea0058a8 100644
--- a/src/soc/amd/picasso/mca.c
+++ b/src/soc/amd/picasso/mca.c
@@ -8,6 +8,7 @@
 #include <console/console.h>
 #include <arch/bert_storage.h>
 #include <cper.h>
+#include <cbmem.h>
 
 struct mca_bank {
 	int bank;
@@ -193,3 +194,31 @@ void check_mca(void)
 	for (i = 0 ; i < num_banks ; i++)
 		wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts);
 }
+
+void bert_reserved_region(void **start, size_t *size)
+{
+	const struct cbmem_entry *bert;
+
+	*start = NULL;
+	*size = 0;
+
+	bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA);
+	if (!bert)
+		return;
+
+	*start = cbmem_entry_start(bert);
+	*size = cbmem_entry_size(bert);
+}
+
+static void alloc_bert_in_cbmem(int unused)
+{
+	void *p;
+
+	if (CONFIG(ACPI_BERT)) {
+		p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, CONFIG_ACPI_BERT_SIZE);
+		if (!p)
+			printk(BIOS_ERR, "Error: BERT region was not added\n");
+	}
+}
+
+ROMSTAGE_CBMEM_INIT_HOOK(alloc_bert_in_cbmem)
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 0c8d9c0cdf..c6fd11874a 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -16,26 +16,6 @@
 #include <soc/iomap.h>
 #include <amdblocks/acpimmio.h>
 
-#if CONFIG(ACPI_BERT)
- #if CONFIG_SMM_TSEG_SIZE == 0x0
-  #define BERT_REGION_MAX_SIZE 0x100000
- #else
-  /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */
-  #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE
- #endif
-#else
- #define BERT_REGION_MAX_SIZE 0
-#endif
-
-void bert_reserved_region(void **start, size_t *size)
-{
-	if (CONFIG(ACPI_BERT))
-		*start = cbmem_top();
-	else
-		start = NULL;
-	*size = BERT_REGION_MAX_SIZE;
-}
-
 void *cbmem_top_chipset(void)
 {
 	msr_t tom = rdmsr(TOP_MEM);
@@ -45,13 +25,12 @@ void *cbmem_top_chipset(void)
 
 	/* 8MB alignment to keep MTRR usage low */
 	return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
-			- CONFIG_SMM_TSEG_SIZE
-			- BERT_REGION_MAX_SIZE, 8*MiB);
+			- CONFIG_SMM_TSEG_SIZE, 8*MiB);
 }
 
 static uintptr_t smm_region_start(void)
 {
-	return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE;
+	return (uintptr_t)cbmem_top();
 }
 
 static size_t smm_region_size(void)