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authorArthur Heymans <arthur@aheymans.xyz>2023-01-30 19:09:34 +0100
committerArthur Heymans <arthur@aheymans.xyz>2023-02-23 08:53:38 +0000
commit829e8e65b93963d15367092cd3d364c230465720 (patch)
treeebcee8a625ed81f6beffe9a0324c713d6a20b9a6
parent6b2b8355b321301f39335246afc0db71496961c3 (diff)
soc/intel: Use common codeflow for MP init
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*: Remove lapic from devicetree). Alderlake cpu code was linked in romstage but unused so drop it. Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
-rw-r--r--src/soc/intel/alderlake/Makefile.inc1
-rw-r--r--src/soc/intel/alderlake/cpu.c2
-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/apollolake/cpu.c9
-rw-r--r--src/soc/intel/apollolake/include/soc/cpu.h1
-rw-r--r--src/soc/intel/cannonlake/cpu.c2
-rw-r--r--src/soc/intel/common/block/cpu/mp_init.c8
-rw-r--r--src/soc/intel/common/block/include/intelblocks/mp_init.h20
-rw-r--r--src/soc/intel/elkhartlake/cpu.c2
-rw-r--r--src/soc/intel/jasperlake/cpu.c2
-rw-r--r--src/soc/intel/meteorlake/cpu.c2
-rw-r--r--src/soc/intel/skylake/cpu.c2
-rw-r--r--src/soc/intel/tigerlake/cpu.c2
-rw-r--r--src/soc/intel/xeon_sp/cpx/chip.c2
-rw-r--r--src/soc/intel/xeon_sp/cpx/cpu.c6
-rw-r--r--src/soc/intel/xeon_sp/skx/chip.c2
-rw-r--r--src/soc/intel/xeon_sp/skx/cpu.c6
17 files changed, 19 insertions, 52 deletions
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index 2055870251..fa52efbc6f 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -22,7 +22,6 @@ romstage-y += espi.c
romstage-y += meminit.c
romstage-y += pcie_rp.c
romstage-y += reset.c
-romstage-y += cpu.c
ramstage-y += acpi.c
ramstage-y += chip.c
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 27c6a9330d..6b9e5e4ca2 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -188,7 +188,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void soc_init_cpus(struct bus *cpu_bus)
+void mp_init_cpus(struct bus *cpu_bus)
{
/* TODO: Handle mp_init_with_smm failure? */
mp_init_with_smm(cpu_bus, &mp_ops);
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 11e3a1e24a..e7a8168c94 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -209,7 +209,7 @@ static struct device_operations pci_domain_ops = {
struct device_operations apl_cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
- .init = apollolake_init_cpus,
+ .init = mp_cpu_bus_init,
.acpi_fill_ssdt = generate_cpu_entries,
};
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 1e0b27b48c..fec2607345 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -262,18 +262,11 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void soc_init_cpus(struct bus *cpu_bus)
+void mp_init_cpus(struct bus *cpu_bus)
{
/* Clear for take-off */
/* TODO: Handle mp_init_with_smm failure? */
mp_init_with_smm(cpu_bus, &mp_ops);
-}
-
-void apollolake_init_cpus(struct device *dev)
-{
- if (!dev->link_list)
- add_more_links(dev, 1);
- soc_init_cpus(dev->link_list);
/* Temporarily cache the memory-mapped boot media. */
if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) &&
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 3157952455..621fe4cbb5 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -8,7 +8,6 @@
#include <soc/msr.h>
struct device;
-void apollolake_init_cpus(struct device *dev);
void mainboard_devtree_update(struct device *dev);
/* Flush L1D to L2 */
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 7e5e4cc0ca..b8a2c8ceb5 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -203,7 +203,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void soc_init_cpus(struct bus *cpu_bus)
+void mp_init_cpus(struct bus *cpu_bus)
{
/* TODO: Handle mp_init_with_smm failure? */
mp_init_with_smm(cpu_bus, &mp_ops);
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 66d74edc00..66890476a9 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -135,16 +135,12 @@ void get_microcode_info(const void **microcode, int *parallel)
* creation of the new node will be skipped. This node will have the APIC ID defined
* in devicetree.
*/
-void init_cpus(void)
+static void init_cpus(void)
{
struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
assert(dev != NULL);
- /* In case link to APIC device is not found, create the one */
- if (!dev->link_list)
- add_more_links(dev, 1);
-
- soc_init_cpus(dev->link_list);
+ mp_cpu_bus_init(dev);
}
static void coreboot_init_cpus(void *unused)
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index 9029c91c45..f7cdf87334 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -24,16 +24,6 @@ int get_cpu_count(void);
void get_microcode_info(const void **microcode, int *parallel);
/*
- * Perform BSP and AP initialization
- * This function can be called in below cases
- * 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude
- * this call if user has selected USE_INTEL_FSP_MP_INIT)
- * 2. coreboot would like to take APs control back after FSP-S has done with MP
- * initialization based on user select USE_INTEL_FSP_MP_INIT
- */
-void init_cpus(void);
-
-/*
* This function will perform any recommended CPU (BSP and AP) initialization
* after coreboot has done the multiprocessor initialization (before FSP-S)
* and prior to coreboot perform post_cpus_init (after DRAM resources are set).
@@ -52,14 +42,4 @@ void before_post_cpus_init(void);
*/
void soc_core_init(struct device *dev);
-/*
- * In this function SOC must fill required mp_ops params, also it
- * should call these mp_ops callback functions by calling
- * mp_init_with_smm() function from x86/mp_init.c file.
- *
- * Also, if there is any other SOC specific functionalities to be
- * implemented before or after MP Init, it can be done here.
- */
-void soc_init_cpus(struct bus *cpu_bus);
-
#endif /* SOC_INTEL_COMMON_BLOCK_MP_INIT_H */
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index 8ba28c0159..49e418a4b5 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -137,7 +137,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void soc_init_cpus(struct bus *cpu_bus)
+void mp_init_cpus(struct bus *cpu_bus)
{
/* TODO: Handle mp_init_with_smm failure? */
mp_init_with_smm(cpu_bus, &mp_ops);
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 24e5aa79f9..8dd2682fbb 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -131,7 +131,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void soc_init_cpus(struct bus *cpu_bus)
+void mp_init_cpus(struct bus *cpu_bus)
{
/* TODO: Handle mp_init_with_smm failure? */
mp_init_with_smm(cpu_bus, &mp_ops);
diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c
index c6d22eef9f..a778381081 100644
--- a/src/soc/intel/meteorlake/cpu.c
+++ b/src/soc/intel/meteorlake/cpu.c
@@ -167,7 +167,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void soc_init_cpus(struct bus *cpu_bus)
+void mp_init_cpus(struct bus *cpu_bus)
{
if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 26ab2712a9..5cf48eaded 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -236,7 +236,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void soc_init_cpus(struct bus *cpu_bus)
+void mp_init_cpus(struct bus *cpu_bus)
{
/* TODO: Handle mp_init_with_smm failure? */
mp_init_with_smm(cpu_bus, &mp_ops);
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index e81a655329..3d0f0e90ad 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -137,7 +137,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void soc_init_cpus(struct bus *cpu_bus)
+void mp_init_cpus(struct bus *cpu_bus)
{
/* TODO: Handle mp_init_with_smm failure? */
mp_init_with_smm(cpu_bus, &mp_ops);
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 21d6e1748e..9d94d8b088 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -49,7 +49,7 @@ static struct device_operations pci_domain_ops = {
static struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
- .init = cpx_init_cpus,
+ .init = mp_cpu_bus_init,
.acpi_fill_ssdt = generate_cpu_entries,
};
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 0e95131824..fefb900943 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -211,7 +211,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void cpx_init_cpus(struct device *dev)
+void mp_init_cpus(struct bus *bus)
{
microcode_patch = intel_microcode_find();
@@ -221,13 +221,13 @@ void cpx_init_cpus(struct device *dev)
intel_microcode_load_unlocked(microcode_patch);
/* TODO: Handle mp_init_with_smm failure? */
- mp_init_with_smm(dev->link_list, &mp_ops);
+ mp_init_with_smm(bus, &mp_ops);
/*
* chip_config is used in cpu device callback. Other than cpu 0,
* rest of the CPU devices do not have chip_info updated.
*/
- chip_config = dev->chip_info;
+ chip_config = bus->dev->chip_info;
/* update numa domain for all cpu devices */
xeonsp_init_cpu_config();
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index 924ce22bf6..a113d5a186 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -35,7 +35,7 @@ static struct device_operations pci_domain_ops = {
static struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
- .init = xeon_sp_init_cpus,
+ .init = mp_cpu_bus_init,
#if CONFIG(HAVE_ACPI_TABLES)
/* defined in src/soc/intel/common/block/acpi/acpi.c */
.acpi_fill_ssdt = generate_cpu_entries,
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index de8eee8022..283cbcc9ae 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -228,7 +228,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void xeon_sp_init_cpus(struct device *dev)
+void mp_init_cpus(struct bus *bus)
{
FUNC_ENTER();
@@ -237,13 +237,13 @@ void xeon_sp_init_cpus(struct device *dev)
* rest of the CPU devices do not have
* chip_info updated. Global chip_config is used as workaround
*/
- chip_config = dev->chip_info;
+ chip_config = bus->dev->chip_info;
config_reset_cpl3_csrs();
/* calls src/cpu/x86/mp_init.c */
/* TODO: Handle mp_init_with_smm failure? */
- mp_init_with_smm(dev->link_list, &mp_ops);
+ mp_init_with_smm(bus, &mp_ops);
/* update numa domain for all cpu devices */
xeonsp_init_cpu_config();