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authorFelix Held <felix-coreboot@felixheld.de>2022-03-28 17:24:52 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-03-30 01:18:02 +0000
commit621a8d69d9c7d5eb86e409e7cdee665eaf845040 (patch)
tree2e619b333b435f76285b8e54f18354e8b87a472c
parent2b4d1480d6afe04cc4065f27abf6fc0c1fa8d9ae (diff)
mb/amd/chausie/devicetree: update PCI root ports
Only enable the PCIe root ports that have corresponding DXIO descriptors and also update the comments to have them match the actual hardware configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I378c620abb6e52de680669b6edd228874153e399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/amd/chausie/devicetree.cb9
1 files changed, 3 insertions, 6 deletions
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 7f37be2128..85e9c08f7e 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -28,12 +28,9 @@ chip soc/amd/sabrina
device domain 0 on
device ref iommu on end
- device ref gpp_bridge_0 on end # NVMe
- device ref gpp_bridge_1 on end
- device ref gpp_bridge_2 on end # WWAN
- device ref gpp_bridge_3 on end # LAN
- device ref gpp_bridge_4 on end # WLAN
- device ref gpp_bridge_5 on end
+ device ref gpp_bridge_0 on end # GBE
+ device ref gpp_bridge_1 on end # WIFI
+ device ref gpp_bridge_2 on end # NVMe SSD
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)