diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-03-30 12:00:35 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-22 08:59:53 +0200 |
| commit | 5d997f9459e95c52ed70f98ab0db2320cf8d6238 (patch) | |
| tree | bb8565fd9fca5826e40e922ce6a43e2f5fdf0b7b | |
| parent | a2c4f9ee9fbedfe540145350b121f5ffb9ce0b67 (diff) | |
imgtec/pistachio: DDR reads return to controller with no bubbles
When the PHY is compiled to run in HDR(half data rate),
then either NOBUB or FXDAT must be set to 1 in the DDR
system general configuration register. NOBUB specifies
that reads should be returned to the controller with
no bubbles and this is felt preferable to the fixed
latency option (FXDAT). Both of them inrease read
latency.
BRANCH=none
BUG=chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly
Change-Id: Iee530ba5bb0acc889fba447dc2ee5cb965ba6926
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7944b4af45d9504098f8b4af44d0f5abafea42c
Original-Change-Id: I9ced76bd670fc4efa7441d57e15f97871b046ae9
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/264341
Original-Reviewed-by: James Hartley <james.hartley@imgtec.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9917
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/soc/imgtec/pistachio/ddr2_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index 66b8778c48..f47b24f348 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -259,7 +259,7 @@ int init_ddr2(void) * 4 LPDLLPD DEf 1 0 * 7:5 DQSGX DQS Extention 000 * 10:8 DQSGE DQS Early Gate - * 11 NOBUB No Bubbles, adds latency 0 + * 11 NOBUB No Bubbles, adds latency 1 * 12 FXDLAT Fixed Read Latency 0 * 15:13 Reserved * 19:16 CKEPDD CKE Power Down 0000 @@ -273,7 +273,7 @@ int init_ddr2(void) * 30 RSTOE RST# Output Enable 1 * 31 CKEOE CKE Output Enable 1 */ - write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000007); + write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000807); /* DTPR0 : DRAM Timing Params 0 * 1:0 tMRD 2 * 4:2 tRTP 3 |