diff options
| author | Roger Wang <roger2.wang@lcfc.corp-partner.google.com> | 2024-11-14 15:56:33 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-22 02:52:06 +0000 |
| commit | 51e3838c780f9cd820dda98a269071a21bdbf555 (patch) | |
| tree | 94392de02653542cd990411eaa4b64b1c28984dc | |
| parent | 307801d8dc292fef9556068e95d7f361449d8a46 (diff) | |
mb/google/nissa/var/pujjoga: Turn off camera during S0ix
Add a variant specific S0ix hook to fill the SSDT table to disable and
enable camera during suspend and resume respectively. For safety concern,
our client LENOVO want us to follow the Boten project to create the function.
BUG=b:378525209
TEST=Build Pujjoga BIOS image. Ensure that camera is disabled during
suspend and enabled during resume. Do the powerd_dbus_suspend and
measure the camera power 3.3V which is disable. And resume will recover.
Change-Id: I7c7f5d314e8b2a4d5f72c452128f6c4b57c45993
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85133
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/pujjoga/variant.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/pujjoga/variant.c b/src/mainboard/google/brya/variants/pujjoga/variant.c index c4a6face5b..2264264c57 100644 --- a/src/mainboard/google/brya/variants/pujjoga/variant.c +++ b/src/mainboard/google/brya/variants/pujjoga/variant.c @@ -2,8 +2,23 @@ #include <fw_config.h> #include <sar.h> +#include <acpi/acpigen.h> +#include <gpio.h> +#include <acpi/acpi.h> +#include <baseboard/variants.h> + const char *get_wifi_sar_cbfs_filename(void) { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); } + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + /* GPP_C3 control the 3.3V of user facing camera, + pull down when do suspend and pull high when resume. */ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(GPP_C3); + else if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(GPP_C3); +} |