diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-09-07 01:33:11 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-13 07:07:47 +0000 |
| commit | 4ba9eeab08d3ab817b7751dc6f834148667ce065 (patch) | |
| tree | 41ade52d3a48afc8056471e872804a1aac0c0cde | |
| parent | 300fbc502be1376f932fb0cccb71eae96a176895 (diff) | |
soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways
The calculation of non-eviction ways (used for cache-as-ram
configuration) has been simplified by removing conditional move
instructions and directly adding the remainder to the quotient.
This achieves the same ceiling operation but with potentially improved
efficiency (less instructions).
No functional changes are expected.
TEST=Able to build and boot google/rex.
Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 90da9e7232..c1af88299d 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -513,13 +513,13 @@ find_llc_subleaf: xor %edx, %edx /* Clear the upper 32-bit of dividend */ div %ecx /* - * Increment data_ways by 1 if RW data size (CONFIG_DCACHE_RAM_SIZE) is + * Effectively ceiling the result if RW data size (CONFIG_DCACHE_RAM_SIZE) is * not divisible by way_size (ECX) */ - movl $0x01, %ecx - cmp $0x00, %edx - cmovne %ecx, %edx - add %edx, %eax + testl %edx, %edx + jz skip_increment + incl %eax +skip_increment: mov %eax, %edx /* back up data_ways in edx */ mov %eax, %ecx movl $0x01, %eax |