diff options
author | Pavan Holla <pholla@chromium.org> | 2024-04-18 14:34:35 +0000 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-22 13:21:01 +0000 |
commit | 48097a17f151bf3843bd921391125ba8de56ac65 (patch) | |
tree | 0cb175f4028dce76e4d2bc8d0c7e5dfc9611b576 | |
parent | 835ed7a7ab5cb00136c45c1964c859dfe32df6fa (diff) |
ec/google/chromeec: Do not fill TypeC ACPI device when UCSI is enabled
Do not fill the ACPI table entry associated with the cros_ec_typec
driver once we switch to the UCSI kernel driver. Skip the ACPI entry if
EC implements the UCSI_PPM feature, and the CBI flag to enable UCSI is
set.
BUG=b:333078787
TEST=emerge-brox coreboot chromeos-bootimage
Cq-Depend: chromium:5416841
Change-Id: I67dff6445aa7ba3ba48a04d1df3541f880d09d0a
Signed-off-by: Pavan Holla <pholla@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
-rw-r--r-- | src/ec/google/chromeec/ec.c | 25 | ||||
-rw-r--r-- | src/ec/google/chromeec/ec.h | 7 | ||||
-rw-r--r-- | src/ec/google/chromeec/ec_acpi.c | 5 |
3 files changed, 37 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 8fdfbfbb28..a32b2a54a4 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -723,6 +723,31 @@ int google_chromeec_cbi_get_ssfc(uint32_t *ssfc) return cbi_get_uint32(ssfc, CBI_TAG_SSFC); } +bool google_chromeec_get_ucsi_enabled(void) +{ + int rv; + union ec_common_control cc; + + rv = google_chromeec_check_feature(EC_FEATURE_UCSI_PPM); + if (rv < 0) { + printk(BIOS_INFO, "Cannot check if EC_FEATURE_UCSI_PPM is available: status = %d\n", rv); + return false; + } + + if (rv == 0) + return false; + + /* Check if PPM is enabled at runtime. */ + cc.ucsi_enabled = 0; + rv = cbi_get_uint32(&cc.raw_value, CBI_TAG_COMMON_CONTROL); + if (rv < 0) { + printk(BIOS_DEBUG, "Cannot get tag CBI_TAG_COMMON_CONTROL from CBI: status = %d\n", rv); + return false; + } + + return (cc.ucsi_enabled != 0); +} + static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) { struct ec_params_get_cbi params = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 0e1df9cf6a..0062df60db 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -424,6 +424,13 @@ void google_chromeec_clear_ec_ap_idle(void); */ bool google_chromeec_is_battery_present_and_above_critical_threshold(void); +/** + * Determine if the UCSI stack is currently active. + * + * @return true if EC implements the UCSI stack + */ +bool google_chromeec_get_ucsi_enabled(void); + #if CONFIG(HAVE_ACPI_TABLES) /** * Writes USB Type-C PD related information to the SSDT diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index cf29636e34..e24f8ac824 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -157,6 +157,11 @@ static void fill_ssdt_typec_device(const struct device *dev) struct acpi_pld pld = {0}; uint32_t pcap_mask = 0; + /* UCSI implementations do not require an ACPI device with mux info since the + linux kernel doesn't set the muxes. */ + if (google_chromeec_get_ucsi_enabled()) + return; + rv = google_chromeec_get_num_pd_ports(&num_ports); if (rv || num_ports == 0) return; |