diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-11-01 15:44:17 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-11-04 08:20:28 +0000 |
| commit | 14d59912f8cdbec7e0121042c43e5728dc361509 (patch) | |
| tree | d573786008c760b20004b22460ab07aae5a188af | |
| parent | 645f244fd08b463b93c50c9d71e3767e1c9ef91a (diff) | |
soc/intel/icelake: Add alignment check for TSEG base and size
This patch ensures to not set SMRR if TSEG base is not align with TSEG size
Change-Id: I77d1cb2fd287f45859cde37a564ea7c147d5633f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36542
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/icelake/smmrelocate.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index edcc49db5e..8f56ad6650 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -178,6 +178,13 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) const u32 rmask = ~(4 * KiB - 1); smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; + } + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ |