diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-07-16 13:26:31 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-07-18 06:01:14 +0000 |
| commit | 0c66434b831c0e9086774944e2b83bc321ad1624 (patch) | |
| tree | 48ae8c9471feebeb929fadb309a86ff5f1837bb6 | |
| parent | e7c926482dcd2ab83d0686ec1decc72f59dcd1da (diff) | |
soc/intel/cmn/pch: Consolidate eSPI.h into IA common code
This patch moves the SoC-specific `eSPI.h` file into the IA common
code to promote code reuse and reduce duplication across different
SoC generations.
TEST=Builds successfully for google/rex.
Change-Id: Icb09421eec45c1ef8ab50252543b000078f18b21
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
| -rw-r--r-- | src/soc/intel/common/pch/include/intelpch/espi.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/common/pch/include/intelpch/espi.h b/src/soc/intel/common/pch/include/intelpch/espi.h new file mode 100644 index 0000000000..f1d35d0566 --- /dev/null +++ b/src/soc/intel/common/pch/include/intelpch/espi.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _INTELPCH_ESPI_H_ +#define _INTELPCH_ESPI_H_ + +/* PCI Configuration Space (D31:F0): ESPI */ +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define SERIRQ_CNTL 0x64 +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1 */ +#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2 */ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) + +#endif /* _INTELPCH_ESPI_H_ */ |