diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-08-27 22:46:48 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-31 06:42:29 +0000 |
| commit | 05ef94795f0303326084290690659f99c6c0e9a7 (patch) | |
| tree | 8f1adbe2f54beccc81c4d4c126d5c990aa386082 | |
| parent | 15d6240c1d08a7f8c356da378bef325e4dd17b80 (diff) | |
soc/amd/picasso/southbridge.h: rename GPP clock setting offsets
The _SHIFT postfix is a bit clearer than the _SHL one and more in line
with the names used for this kind of defines in coreboot. The
documentation on that register is currently wrong and will hopefully be
fixed in the future; the defines should now match the hardware.
BUG=b:149970243
BRANCH=zork
Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 4f06dd7f2e..b5792139da 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -139,12 +139,14 @@ /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 -#define GPP_CLK0_REQ_SHL 0 -#define GPP_CLK1_REQ_SHL 2 -#define GFX_CLK0_REQ_SHL 4 -#define GPP_CLK2_REQ_SHL 6 -#define GPP_CLK3_REQ_SHL 8 -#define GFX_CLK1_REQ_SHL 10 +#define GPP_CLK0_REQ_SHIFT 0 +#define GPP_CLK1_REQ_SHIFT 2 +#define GPP_CLK4_REQ_SHIFT 4 +#define GPP_CLK2_REQ_SHIFT 6 +#define GPP_CLK3_REQ_SHIFT 8 +#define GPP_CLK5_REQ_SHIFT 10 +#define GPP_CLK6_REQ_SHIFT 12 +#define GPP_CLK_OUTPUT_COUNT 7 #define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) |