via: Start template for VIA C7 w/ CX700 northbridge

The first steps to bring C7 and CX700 support back mainline. Most is
skeleton copied from the `min86' example.

The romstage entry is placed in the northbridge code, as that's where
we'll perform raminit. Support to read the FSB frequency is added right
away, same for a reset function (using CF9 reset), as both are required
for a minimal build test.

A mainboard VIA EPIA-EX is also introduced for build testing, and in
later stages boot testing as well.

Links:
DS: https://theretroweb.com/chip/documentation/via-cx700-datasheet-feb06-666c8b172d347554179891.pdf
PM: https://web.archive.org/web/20180616220857/http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221

Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

20 files changed, 207 insertions, 0 deletions

diff --git a/src/cpu/Makefile.mk b/src/cpu/Makefile.mk
index af2402742f..0afe454c1e 100644
--- a/src/cpu/Makefile.mk
+++ b/src/cpu/Makefile.mk
@@ -6,6 +6,7 @@
 subdirs-y += amd
 subdirs-y += armltd
 subdirs-y += intel
+subdirs-y += via
 subdirs-$(CONFIG_ARCH_X86) += x86
 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
 subdirs-$(CONFIG_CPU_POWER9) += power9
diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig
new file mode 100644
index 0000000000..20f7c95a16
--- /dev/null
+++ b/src/cpu/via/Kconfig
@@ -0,0 +1 @@
+source "src/cpu/via/*/Kconfig"
diff --git a/src/cpu/via/Makefile.mk b/src/cpu/via/Makefile.mk
new file mode 100644
index 0000000000..e8b7820bdf
--- /dev/null
+++ b/src/cpu/via/Makefile.mk
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+subdirs-$(CONFIG_CPU_VIA_C7) += c7
diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig
new file mode 100644
index 0000000000..df81b3f84e
--- /dev/null
+++ b/src/cpu/via/c7/Kconfig
@@ -0,0 +1,17 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config CPU_VIA_C7
+	bool
+	select ARCH_X86
+	select NO_SMM
+	select SSE2
+	select UNKNOWN_TSC_RATE
+	select UDELAY_LAPIC
+	select LAPIC_MONOTONIC_TIMER
+
+if CPU_VIA_C7
+
+config DCACHE_BSP_STACK_SIZE
+	default 0x1000
+
+endif
diff --git a/src/cpu/via/c7/Makefile.mk b/src/cpu/via/c7/Makefile.mk
new file mode 100644
index 0000000000..0890cee18b
--- /dev/null
+++ b/src/cpu/via/c7/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y	+= ../car/cache_as_ram.S
+bootblock-y	+= ../../intel/car/bootblock.c
+
+postcar-y	+= ../car/exit_car.S
diff --git a/src/cpu/via/car/cache_as_ram.S b/src/cpu/via/car/cache_as_ram.S
new file mode 100644
index 0000000000..5c5066d7ea
--- /dev/null
+++ b/src/cpu/via/car/cache_as_ram.S
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+.section .init, "ax", @progbits
+
+.global bootblock_pre_c_entry
+
+.code32
+bootblock_pre_c_entry:
+	call	bootblock_c_entry_bist
+
+.Lhlt:
+	hlt
+	jmp	.Lhlt
diff --git a/src/cpu/via/car/exit_car.S b/src/cpu/via/car/exit_car.S
new file mode 100644
index 0000000000..0f1b227c2d
--- /dev/null
+++ b/src/cpu/via/car/exit_car.S
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+.global chipset_teardown_car
+
+.code32
+chipset_teardown_car:
+	/* Return to caller. */
+	jmp	*%esp
diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig
new file mode 100644
index 0000000000..8fff54262d
--- /dev/null
+++ b/src/mainboard/via/Kconfig
@@ -0,0 +1,17 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if VENDOR_VIA
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/via/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/via/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "VIA"
+
+endif # VENDOR_VIA
diff --git a/src/mainboard/via/Kconfig.name b/src/mainboard/via/Kconfig.name
new file mode 100644
index 0000000000..c3d6cfddb4
--- /dev/null
+++ b/src/mainboard/via/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config VENDOR_VIA
+	bool "VIA"
diff --git a/src/mainboard/via/epia-ex/Kconfig b/src/mainboard/via/epia-ex/Kconfig
new file mode 100644
index 0000000000..76347f2621
--- /dev/null
+++ b/src/mainboard/via/epia-ex/Kconfig
@@ -0,0 +1,18 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_VIA_EPIA_EX
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select CPU_VIA_C7
+	select NORTHBRIDGE_VIA_CX700
+	select BOARD_ROMSIZE_KB_512
+	select NO_UART_ON_SUPERIO
+
+config MAINBOARD_DIR
+	default "via/epia-ex"
+
+config MAINBOARD_PART_NUMBER
+	default "EPIA-EX"
+
+endif
diff --git a/src/mainboard/via/epia-ex/Kconfig.name b/src/mainboard/via/epia-ex/Kconfig.name
new file mode 100644
index 0000000000..067e6b4813
--- /dev/null
+++ b/src/mainboard/via/epia-ex/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_VIA_EPIA_EX
+	bool "EPIA-EX (work in progress)"
diff --git a/src/mainboard/via/epia-ex/board_info.txt b/src/mainboard/via/epia-ex/board_info.txt
new file mode 100644
index 0000000000..b2367999a8
--- /dev/null
+++ b/src/mainboard/via/epia-ex/board_info.txt
@@ -0,0 +1,8 @@
+Board name: EPIA-EX
+Category: mini
+Board URL: https://web.archive.org/web/20211129175218/https://www.viatech.com/en/support/eol/epia-ex-eol/
+ROM package: PLCC
+ROM protocol: LPC
+ROM socketed: y
+Flashrom support: y
+Release year: 2006
diff --git a/src/mainboard/via/epia-ex/devicetree.cb b/src/mainboard/via/epia-ex/devicetree.cb
new file mode 100644
index 0000000000..3f76279175
--- /dev/null
+++ b/src/mainboard/via/epia-ex/devicetree.cb
@@ -0,0 +1,6 @@
+chip northbridge/via/cx700
+
+	device domain 0 on
+	end
+
+end
diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig
new file mode 100644
index 0000000000..95f289aacb
--- /dev/null
+++ b/src/northbridge/via/cx700/Kconfig
@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config NORTHBRIDGE_VIA_CX700
+	bool
+	select PCI
+	select NO_ECAM_MMCONF_SUPPORT
+	select HAVE_CF9_RESET
+
+if NORTHBRIDGE_VIA_CX700
+
+config CHIPSET_DEVICETREE
+	default "northbridge/via/cx700/chipset.cb"
+
+endif
diff --git a/src/northbridge/via/cx700/Makefile.mk b/src/northbridge/via/cx700/Makefile.mk
new file mode 100644
index 0000000000..550ee2dec3
--- /dev/null
+++ b/src/northbridge/via/cx700/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_NORTHBRIDGE_VIA_CX700),y)
+
+romstage-y	+= romstage.c
+ramstage-y	+= chip.c
+all-y		+= clock.c reset.c
+
+endif
diff --git a/src/northbridge/via/cx700/chip.c b/src/northbridge/via/cx700/chip.c
new file mode 100644
index 0000000000..57583b84c7
--- /dev/null
+++ b/src/northbridge/via/cx700/chip.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+struct chip_operations northbridge_via_cx700_ops = { NULL };
diff --git a/src/northbridge/via/cx700/chipset.cb b/src/northbridge/via/cx700/chipset.cb
new file mode 100644
index 0000000000..4dd11f307e
--- /dev/null
+++ b/src/northbridge/via/cx700/chipset.cb
@@ -0,0 +1,17 @@
+chip northbridge/via/cx700
+
+	device domain 0 on
+
+		device pci 00.0 alias host_ctrl	on  end
+		device pci 00.1 alias host_err	on  end
+		device pci 00.2 alias host_if	on  end
+		device pci 00.3 alias dram_ctrl	on  end
+		device pci 00.4 alias pm_ctrl	on  end
+		device pci 00.7 alias north_end	on  end
+		device pci 01.0 alias north_pci	off
+			device pci 00.0 alias vga off end
+		end
+
+	end
+
+end
diff --git a/src/northbridge/via/cx700/clock.c b/src/northbridge/via/cx700/clock.c
new file mode 100644
index 0000000000..6bd5942a93
--- /dev/null
+++ b/src/northbridge/via/cx700/clock.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define __SIMPLE_DEVICE__
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <static_devices.h>
+#include <delay.h>
+
+static unsigned int read_timer_fsb(void)
+{
+	/* Allows access to all northbridge PCI devfn's */
+	pci_write_config8(_sdev_host_ctrl, 0x4f, 0x01);
+
+	const u8 misc_1 = pci_read_config8(_sdev_host_if, 0x54);
+	switch (misc_1 >> 5) {
+	case 0:
+		return 100;
+	case 1:
+		return 133;
+	case 2:
+		return 166;
+	case 3:
+		return 200;
+	default:
+		printk(BIOS_WARNING, "Unknown FSB frequency encoding: 0x%x\n", misc_1 >> 5);
+		return 200;
+	}
+}
+
+u32 get_timer_fsb(void)
+{
+	static unsigned int fsb_mhz;
+
+	if (!fsb_mhz)
+		fsb_mhz = read_timer_fsb();
+
+	return fsb_mhz;
+}
diff --git a/src/northbridge/via/cx700/reset.c b/src/northbridge/via/cx700/reset.c
new file mode 100644
index 0000000000..b052f1d8d5
--- /dev/null
+++ b/src/northbridge/via/cx700/reset.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <reset.h>
+#include <cf9_reset.h>
+
+void do_board_reset(void)
+{
+	full_reset();
+}
diff --git a/src/northbridge/via/cx700/romstage.c b/src/northbridge/via/cx700/romstage.c
new file mode 100644
index 0000000000..f4c5584c30
--- /dev/null
+++ b/src/northbridge/via/cx700/romstage.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <romstage_common.h>
+#include <halt.h>
+
+void __noreturn romstage_main(void)
+{
+	/* Needed for __noreturn */
+	halt();
+}