diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2018-11-22 16:26:18 +0530 |
---|---|---|
committer | Subrata Banik <subrata.banik@intel.com> | 2018-11-26 05:47:49 +0000 |
commit | 9df0440c6cd0031c81d15ed10df68a94fc43bac6 (patch) | |
tree | d27696e69655e5d6f9d572ae2bad5e812dcfc61c | |
parent | a6634f1f78da9d05082f94f2c86f5ab15adf0d40 (diff) |
soc/intel/icelake: Add support to enable/disable USB charging in s3/S5
Change-Id: I0559b8a546f7a67759377c7f51b2faa2280aa797
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29793
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/soc/intel/icelake/acpi/globalnvs.asl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/icelake/acpi/globalnvs.asl index 678ce5ac23..b8f4d2fff6 100644 --- a/src/soc/intel/icelake/acpi/globalnvs.asl +++ b/src/soc/intel/icelake/acpi/globalnvs.asl @@ -48,8 +48,34 @@ Field (GNVS, ByteAcc, NoLock, Preserve) U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume + S5U0, 8, // 0x30 - Enable USB in S5 + S3U0, 8, // 0x31 - Enable USB in S3 /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> } + +/* Set flag to enable USB charging in S3 */ +Method (S3UE) +{ + Store (One, \S3U0) +} + +/* Set flag to disable USB charging in S3 */ +Method (S3UD) +{ + Store (Zero, \S3U0) +} + +/* Set flag to enable USB charging in S5 */ +Method (S5UE) +{ + Store (One, \S5U0) +} + +/* Set flag to disable USB charging in S5 */ +Method (S5UD) +{ + Store (Zero, \S5U0) +} |