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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-12-05 14:33:07 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-06 15:09:17 +0000 |
| commit | 8cb5ea7879cf82b79ab9a2c4342c542a167943bf (patch) | |
| tree | 8632fbe4f09a268471c1d5485a6978c85f09e5be | |
| parent | 879ea7fce8a21359ad80e4008c41587b3e1769ae (diff) | |
nb/i945: Fix typo
Change-Id: I082ac2c1c13cbe6835a02d703f8651e837a43f37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/northbridge/intel/i945/memmap.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 000ac7e682..54141205ec 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -55,7 +55,7 @@ static uintptr_t northbridge_get_tseg_base(void) else tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; - /* subsctract TSEG size */ + /* subtract TSEG size */ tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); return tom; } |