sb,soc/intel: Replace smm_southbridge_enable_smi()

Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

17 files changed, 65 insertions, 25 deletions

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 4778943cf2..e621638da0 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -745,7 +745,7 @@ static void post_mp_init(void)
 {
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	smm_southbridge_enable_smi();
+	global_smi_enable();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index 62c26e3ffa..3404e7fb4a 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -79,7 +79,7 @@ static void post_mp_init(void)
 {
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	smm_southbridge_enable_smi();
+	global_smi_enable();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index 4b2e6071db..b4bfce3f50 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -302,7 +302,7 @@ static void post_mp_init(void)
 {
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	smm_southbridge_enable_smi();
+	global_smi_enable();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index c6844a205b..e69d4fa8da 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -528,7 +528,7 @@ static void post_mp_init(void)
 {
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	smm_southbridge_enable_smi();
+	global_smi_enable();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h
index cf621aad93..07fe0381a1 100644
--- a/src/include/cpu/intel/smm_reloc.h
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -43,7 +43,6 @@ void smm_relocate(void);
  * for clearing the state in the SMM registers. The other is for enabling
  * SMIs. They are split so that other work between the 2 actions. */
 void smm_southbridge_clear_state(void);
-void smm_southbridge_enable_smi(void);
 
 /* To be removed. */
 void smm_initialize(void);
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index fbbd84ac1b..59002619df 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -178,6 +178,11 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
 	smm_state->smbase = staggered_smbase;
 }
 
+static void post_mp_init(void)
+{
+	global_smi_enable();
+}
+
 static const struct mp_ops mp_ops = {
 	.pre_mp_init = pre_mp_init,
 	.get_cpu_count = get_cpu_count,
@@ -186,7 +191,7 @@ static const struct mp_ops mp_ops = {
 	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = relocation_handler,
-	.post_mp_init = smm_southbridge_enable_smi,
+	.post_mp_init = post_mp_init,
 };
 
 void baytrail_init_cpus(struct device *dev)
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index 38efe2ba39..58238db627 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -70,9 +70,8 @@ static void smm_southcluster_route_gpios(void)
 	outl(alt_gpio_reg, alt_gpio_smi);
 }
 
-void smm_southbridge_enable_smi(void)
+static void smm_southbridge_enable(uint16_t pm1_events)
 {
-	uint16_t pm1_events = PWRBTN_EN | GBL_EN;
 
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
@@ -94,6 +93,11 @@ void smm_southbridge_enable_smi(void)
 	enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
 }
 
+void global_smi_enable(void)
+{
+	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
+}
+
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 {
 	/*
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 19cc546239..861f160eb8 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -188,6 +188,11 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t stagger
 	smm_state->smbase = staggered_smbase;
 }
 
+static void post_mp_init(void)
+{
+	global_smi_enable();
+}
+
 static const struct mp_ops mp_ops = {
 	.pre_mp_init         = pre_mp_init,
 	.get_cpu_count       = get_cpu_count,
@@ -196,7 +201,7 @@ static const struct mp_ops mp_ops = {
 	.pre_mp_smm_init     = smm_southbridge_clear_state,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler  = relocation_handler,
-	.post_mp_init        = smm_southbridge_enable_smi,
+	.post_mp_init        = post_mp_init,
 };
 
 void soc_init_cpus(struct device *dev)
diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c
index 5be4346661..e3ebc32304 100644
--- a/src/soc/intel/braswell/smm.c
+++ b/src/soc/intel/braswell/smm.c
@@ -70,9 +70,8 @@ static void smm_southcluster_route_gpios(void)
 	outl(alt_gpio_reg, alt_gpio_smi);
 }
 
-void smm_southbridge_enable_smi(void)
+static void smm_southbridge_enable(uint16_t pm1_events)
 {
-	uint16_t pm1_events = PWRBTN_EN | GBL_EN;
 
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
@@ -96,6 +95,11 @@ void smm_southbridge_enable_smi(void)
 	enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
 }
 
+void global_smi_enable(void)
+{
+	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
+}
+
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 {
 	/*
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 859db7f1ec..4bfa15d354 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -494,7 +494,7 @@ static void post_mp_init(void)
 
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	smm_southbridge_enable_smi();
+	global_smi_enable();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();
diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c
index 1d3860a982..939815a998 100644
--- a/src/soc/intel/broadwell/smi.c
+++ b/src/soc/intel/broadwell/smi.c
@@ -32,11 +32,11 @@ void smm_southbridge_clear_state(void)
 	clear_gpe_status();
 }
 
-void smm_southbridge_enable_smi(void)
+static void smm_southbridge_enable(uint16_t pm1_events)
 {
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	/* Configure events */
-	enable_pm1(PWRBTN_EN | GBL_EN);
+	enable_pm1(pm1_events);
 	disable_gpe(PME_B0_EN);
 
 	/* Enable SMI generation:
@@ -50,6 +50,11 @@ void smm_southbridge_enable_smi(void)
 	enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
 }
 
+void global_smi_enable(void)
+{
+	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
+}
+
 static void __unused southbridge_trigger_smi(void)
 {
 	/**
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index 325a4a75e6..9764a3edbb 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -246,7 +246,7 @@ static void post_mp_init(void)
 	 * Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing.
 	 */
-	smm_southbridge_enable_smi();
+	global_smi_enable();
 }
 
 /*
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c
index 6ef06d483a..b4970adf9d 100644
--- a/src/soc/intel/denverton_ns/smm.c
+++ b/src/soc/intel/denverton_ns/smm.c
@@ -33,12 +33,12 @@ void smm_southbridge_clear_state(void)
 	clear_pmc_status();
 }
 
-void smm_southbridge_enable_smi(void)
+static void smm_southbridge_enable(uint16_t pm1_events)
 {
 
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	/* Configure events Disable PCIe wake. */
-	enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
+	enable_pm1(pm1_events | PCIEXPWAK_DIS);
 	disable_gpe(PME_B0_EN);
 
 	/* Enable SMI generation:
@@ -52,6 +52,11 @@ void smm_southbridge_enable_smi(void)
 	enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
 }
 
+void global_smi_enable(void)
+{
+	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
+}
+
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 {
 	/*
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index e2724cef90..386401f7e3 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -152,6 +152,12 @@ static void post_mp_init(void)
 {
 	/* Set Max Ratio */
 	set_max_turbo_freq();
+
+	/*
+	 * TODO: Now that all APs have been relocated as well as the BSP let SMIs
+	 * start flowing.
+	 */
+	if (0) global_smi_enable();
 }
 
 static const struct mp_ops mp_ops = {
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index a931094669..f97c37da08 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -199,6 +199,7 @@ static void post_mp_init(void)
 	 * TODO: Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing.
 	 */
+	if (0) global_smi_enable();
 }
 
 /*
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index e5af3f136d..9bf763d75b 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -17,10 +17,9 @@ u16 get_pmbase(void)
 	return lpc_get_pmbase();
 }
 
-void smm_southbridge_enable_smi(void)
+static void smm_southbridge_enable(uint16_t pm1_events)
 {
 	u32 smi_en;
-	u16 pm1_en;
 	u32 gpe0_en;
 
 	if (CONFIG(ELOG))
@@ -49,10 +48,7 @@ void smm_southbridge_enable_smi(void)
 	gpe0_en &= ~PME_B0_EN;
 	write_pmbase32(GPE0_EN, gpe0_en);
 
-	pm1_en = 0;
-	pm1_en |= PWRBTN_EN;
-	pm1_en |= GBL_EN;
-	write_pmbase16(PM1_EN, pm1_en);
+	write_pmbase16(PM1_EN, pm1_events);
 
 	/* Enable SMI generation:
 	 *  - on TCO events
@@ -75,6 +71,11 @@ void smm_southbridge_enable_smi(void)
 	write_pmbase32(SMI_EN, smi_en);
 }
 
+void global_smi_enable(void)
+{
+	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
+}
+
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 {
 	/*
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index cddada1d18..df48d864d4 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -35,11 +35,11 @@ void smm_southbridge_clear_state(void)
 	clear_gpe_status();
 }
 
-void smm_southbridge_enable_smi(void)
+static void smm_southbridge_enable(uint16_t pm1_events)
 {
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	/* Configure events */
-	enable_pm1(PWRBTN_EN | GBL_EN);
+	enable_pm1(pm1_events);
 	disable_gpe(PME_B0_EN);
 
 	/* Enable SMI generation:
@@ -53,6 +53,11 @@ void smm_southbridge_enable_smi(void)
 	enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
 }
 
+void global_smi_enable(void)
+{
+	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
+}
+
 static void  __unused southbridge_trigger_smi(void)
 {
 	/**