diff options
| author | Tom Warren <twarren@nvidia.com> | 2014-08-18 13:18:58 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-27 08:03:18 +0100 |
| commit | c65d8c48df9954b7a298de72b08b71fef92472d5 (patch) | |
| tree | 7f4e8594d218b1d037e71b748a6657967cbab5cc | |
| parent | 2152e85e12413532f2c5d4281267c0a5f604211c (diff) | |
tegra132: separate/refactor clock enable/reset code
Added distinct functions for clock_enable and clock_clear_reset,
and rewrote clock_enable_clear_reset() to use them. Useful when
unpowergating SOR partition, for instance, where we need to
enable a bunch of periph clocks, unclamp SOR, then take all of
those periphs out of reset.
BUG=none
BRANCH=none
TEST=none, built rush/ryu OK.
Change-Id: I92edf3104adc8eb7637c47a5e000788fd55f1452
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fd76a6d0d0fb7922c6beacbc1cfcb365b6537b2
Original-Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212916
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8991
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/soc/nvidia/tegra132/clock.c | 18 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/clock.h | 2 |
2 files changed, 16 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index ed5afbaa45..caeb24a9a1 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -584,7 +584,7 @@ void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, writel(val, rst_dev_clr_reg); } -void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) +void clock_enable(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) { if (l) writel(l, &clk_rst->clk_enb_l_set); @@ -598,10 +598,10 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) writel(w, &clk_rst->clk_enb_w_set); if (x) writel(x, &clk_rst->clk_enb_x_set); +} - /* Give clocks time to stabilize. */ - udelay(IO_STABILIZATION_DELAY); - +void clock_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) +{ if (l) writel(l, &clk_rst->rst_dev_l_clr); if (h) @@ -616,6 +616,16 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) writel(x, &clk_rst->rst_dev_x_clr); } +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) +{ + clock_enable(l, h, u, v, w, x); + + /* Give clocks time to stabilize. */ + udelay(IO_STABILIZATION_DELAY); + + clock_clear_reset(l, h, u, v, w, x); +} + void clock_reset_l(u32 bit) { writel(bit, &clk_rst->rst_dev_l_set); diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h index 6f98e3c618..494f28d4db 100644 --- a/src/soc/nvidia/tegra132/include/soc/clock.h +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -292,6 +292,8 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 same_freq); void clock_cpu0_config(void); void clock_halt_avp(void); +void clock_enable(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); +void clock_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg); void clock_reset_l(u32 l); |