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authorKevin Chiu <Kevin.Chiu@quantatw.com>2020-08-12 09:48:11 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-08-17 06:39:38 +0000
commitbed09654420e54b84abb3724f0f7a758a008678d (patch)
treecbf0aaf51d66fa003ad91bf084f9d3ac237232dd
parenteb9337c9cc2fd5432d79509174efdcf6bbcf9a01 (diff)
mb/google/zork: adjust i2c2 data hold time for TP
current setting got 0.278us which is less than the min 0.3us. increase i2c2 data hold time for TP. BUG=b:163613330 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. data hold time measured by scope: 0.3805us Change-Id: I2d564983383c17ed43cc5cc5aaff0fcd67ce6928 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/mainboard/google/zork/variants/berknip/overridetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb
index f0f92c5a31..aa248b682f 100644
--- a/src/mainboard/google/zork/variants/berknip/overridetree.cb
+++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb
@@ -27,6 +27,7 @@ chip soc/amd/picasso
.speed = I2C_SPEED_FAST,
.rise_time_ns = 3,
.fall_time_ns = 2,
+ .data_hold_time_ns = 400,
}"
# Enable I2C3 for H1 400kHz