diff options
| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-10-27 15:07:00 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-11-04 22:09:46 +0000 |
| commit | 3a2867329392a5f332cf1d144f093d5f965ac530 (patch) | |
| tree | e7669660a00ec2b4ba19cb1754291a29888c1e69 | |
| parent | 0dd8fe7ec3c1b767ef228815a24cbb265802b9f4 (diff) | |
mb/asrock/h110m/devicetree: fix VR config info
Removes unnecessary information about the Ring Sliced VR configuration
from another board with FSP1.1 (which is no longer supported).
Change-Id: Ia2b90d9ede782852c2127da972333bada378b217
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/mainboard/asrock/h110m/devicetree.cb | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 2d6b951de4..bd51e40bf3 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -82,21 +82,21 @@ chip soc/intel/skylake # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax* | 0 | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ - # * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c + # VR Settings Configuration + #+----------------+-------+-------+-------------+-------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax* | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------+ + # * - is set automatically in the vr_config.c register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = VR_CFG_AMP(20), \ |