diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-11-29 16:46:49 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-05 14:07:57 +0000 |
| commit | ad41f5512306d118047d2f7243678ddb32b4b06b (patch) | |
| tree | 3c462fefc8006a67a20e9324b6a901c1ba342984 | |
| parent | 378ec8b0de5216b18ab5f2ca2f1ee0b0c29888ea (diff) | |
google/sarien: Increase BIOS region to 28MB
Platform have a 32MB SPI chip, so we can increase the bios region from
16MB to 28MB.
BUG=b:119267832
TEST=Build and boot fine on sarien platform.
Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
| -rw-r--r-- | src/mainboard/google/sarien/chromeos.fmd | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 663176978f..ef97ab8234 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -1,11 +1,11 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1000000 { + SI_ALL@0x0 0x400000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 SI_GBE@0x101000 0x2000 - SI_ME@0x103000 0xefd000 + SI_ME@0x103000 0x2fd000 } - SI_BIOS@0x1000000 0x1000000 { + SI_BIOS@0x400000 0x1c00000 { RW_SECTION_A@0x0 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 @@ -30,8 +30,8 @@ FLASH@0xfe000000 0x2000000 { RW_NVRAM@0x2a000 0x6000 } CONSOLE@0x530000 0x20000 - RW_LEGACY(CBFS)@0x550000 0x6b0000 - WP_RO@0xc00000 0x400000 { + RW_LEGACY(CBFS)@0x550000 0x12b0000 + WP_RO@0x1800000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { |