diff options
| author | Duncan Laurie <dlaurie@google.com> | 2020-11-05 10:06:17 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-11-20 00:25:46 +0000 |
| commit | 98a9f1f61de45fdf936d51342c6a2f06e1980c58 (patch) | |
| tree | 0f96dca4402057850dc3456f604164d262b868c3 | |
| parent | 7d9713674956bbd055631d6fe5f67922a5823c3a (diff) | |
mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device
There is an issue with the storage device being mis-detected on exit
from S0ix which is causing the root device to disappear if the power
is actually turned off via RTD3.
To work around this read the RX state of the pin and apply the IOSSTATE
setting to drive a 0 or 1 back to the internal controller. This will
ensure the device is detected the same on resume as on initial boot.
BUG=b:171993054
TEST=boot on volteer with PCIe NVMe and SATA SSD installed in the M.2
slot and ensure this pin is configured appropriately. Additionally
test with PCIe RTD3 enabled to ensure suspend/resume works reliably.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I85542151eebd0ca411e2c70d8267a8498becee78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/volteer/mainboard.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 0850e745db..ea9e08f294 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -7,6 +7,8 @@ #include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> #include <fw_config.h> +#include <gpio.h> +#include <intelblocks/gpio.h> #include <security/tpm/tss.h> #include <soc/gpio.h> #include <soc/pci_devs.h> @@ -136,6 +138,25 @@ static void mainboard_chip_init(void *chip_info) override_pads = variant_override_gpio_table(&override_num); gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + /* + * Check SATAXPCIE1 (GPP_A12) RX status to determine if SSD is NVMe or SATA and set + * the IOSSTATE RX field to drive 0 or 1 back to the internal controller to ensure + * the attached device is not mis-detected on resume from S0ix. + */ + if (gpio_get(GPP_A12)) { + const struct pad_config gpio_pedet_nvme[] = { + PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx1), + }; + gpio_configure_pads(gpio_pedet_nvme, ARRAY_SIZE(gpio_pedet_nvme)); + printk(BIOS_INFO, "SATAXPCIE1 indicates PCIe NVMe is present\n"); + } else { + const struct pad_config gpio_pedet_sata[] = { + PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx0), + }; + gpio_configure_pads(gpio_pedet_sata, ARRAY_SIZE(gpio_pedet_sata)); + printk(BIOS_INFO, "SATAXPCIE1 indicates SATA SSD is present\n"); + } } void mainboard_silicon_init_params(FSP_S_CONFIG *params) |