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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-11-02 12:14:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-11 10:26:11 +0000 |
| commit | 93d215cb05a05464fef14f26f638341da2ce3d59 (patch) | |
| tree | 9e33a2efb7e6c5a0cb6e90d9f186e73074718b28 | |
| parent | b4d960b65aa126d4534189672322ec62dcd87bde (diff) | |
soc/intel/cannonlake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.
Change-Id: Ifc128099185a2c40ec3e7c5f84fcc42227c93f28
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/cannonlake/pmutil.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index a543861406..428a89fe4b 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -172,6 +172,11 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t)pmc_mmio_regs(); } +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config; |