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| author | Angel Pons <th3fanbus@gmail.com> | 2019-01-04 00:38:43 +0100 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-01-04 13:12:00 +0000 |
| commit | 782341dd3adaa8ecd03af895b84898a603ab2996 (patch) | |
| tree | 39e62a68944a1a36057ab7a3a8e80de0a815e1fb | |
| parent | 98a917443efa7429dd92b073e00876cfb274a058 (diff) | |
util/autoport/readme.md: Correct minor inconsistency
Commit a5072af67d85 ("util/autoport: Use romstage.c instead of
early_southbridge.c") changed where the SPD map is. Reflect that.
Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30655
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | util/autoport/readme.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 67a2c56994..226fcda590 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -80,7 +80,7 @@ If you're able to use full memory with any combination of inserted modules than most likely correct. In order to initialize the memory coreboot needs to know RAM timings. For socketed RAM it's stored in a small EEPROM chip which can be accessed through SPD. Unfortunately mapping between SPD addresses and RAM slots differs and cannot always be detected automatically. -Resulting SPD map is encoded in function `mainboard_get_spd` in `early_southbridge.c`. +Resulting SPD map is encoded in function `mainboard_get_spd` in `romstage.c`. autoport uses the most common map `0x50, 0x51, 0x52, 0x53` except for lenovos which are known to use `0x50, 0x52, 0x51, 0x53`. To detect the correct memory map the easiest way is with vendor BIOS to boot with just one module in channel 0 slot 0 and then see where does it show |