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authorChris Wang <chris.wang@amd.corp-partner.google.com>2020-08-26 13:59:12 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-09-28 09:25:46 +0000
commit6dbf4c8f031a13b1235c60eaca5757ce71aafa68 (patch)
treeb1667dec66706628f9845f7d2e932875141af87a
parent19e22f554e048edaca3ac56a4cf6d8698026e045 (diff)
mb/google/vilboz: update telemetry settings
update the telemetry setting for second SDLE testing(for APU power adjusting). Those values are used to power calibration the APU power and achieving the best performance. BUG=b:160698427 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44804 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/zork/variants/vilboz/overridetree.cb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
index d415de59c9..3d9ff7c01b 100644
--- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
@@ -18,10 +18,10 @@ chip soc/amd/picasso
# End : OPN Performance Configuration
- register "telemetry_vddcr_vdd_slope" = "32453" #mA
- register "telemetry_vddcr_vdd_offset" = "168"
- register "telemetry_vddcr_soc_slope" = "22644" #mA
- register "telemetry_vddcr_soc_offset" = "-70"
+ register "telemetry_vddcr_vdd_slope" = "32643" #mA
+ register "telemetry_vddcr_vdd_offset" = "208"
+ register "telemetry_vddcr_soc_slope" = "22742" #mA
+ register "telemetry_vddcr_soc_offset" = "-83"
# USB OC pin mapping
register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1