diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-11-06 17:11:05 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-11-06 17:11:05 +0000 |
| commit | d63085b20ef40caae1c60a7532b5243e1e30b109 (patch) | |
| tree | c732b7666d8082775022592eeddedff81375eeef | |
| parent | eeec0ef00a6be64d6846599fe7cf81ead22e2f02 (diff) | |
Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.
Since we have CBFS setting rom_address in board files is no longer
necessary.
Also, drop vga_rom_address from RS690 completely, it was never used
in the code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
73 files changed, 0 insertions, 125 deletions
diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb index 69e3467123..a40bf65b7d 100644 --- a/src/mainboard/amd/dbm690t/Config.lb +++ b/src/mainboard/amd/dbm690t/Config.lb @@ -157,7 +157,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb index 2e89c13aaf..10de5c16c8 100644 --- a/src/mainboard/amd/dbm690t/devicetree.cb +++ b/src/mainboard/amd/dbm690t/devicetree.cb @@ -22,7 +22,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb index 6ada7d636e..146ab50bf9 100644 --- a/src/mainboard/amd/pistachio/Config.lb +++ b/src/mainboard/amd/pistachio/Config.lb @@ -158,7 +158,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb index ec16256b26..ab915764b3 100644 --- a/src/mainboard/amd/pistachio/devicetree.cb +++ b/src/mainboard/amd/pistachio/devicetree.cb @@ -23,7 +23,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb index 276b4704b3..7df39865fe 100644 --- a/src/mainboard/arima/hdama/Config.lb +++ b/src/mainboard/arima/hdama/Config.lb @@ -179,7 +179,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end # LAN chip drivers/pci/onboard device pci 6.0 on end # ATI Rage XL - register "rom_address" = "0xfff80000" end ## PCI Slot 5 (correct?) #chip drivers/generic/generic diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb index 2552e18cf7..ac09e730ae 100644 --- a/src/mainboard/arima/hdama/devicetree.cb +++ b/src/mainboard/arima/hdama/devicetree.cb @@ -75,7 +75,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end # LAN chip drivers/pci/onboard device pci 6.0 on end # ATI Rage XL - register "rom_address" = "0xfff80000" end ## PCI Slot 5 (correct?) #chip drivers/generic/generic diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb index f344b466fb..65e2fd4c0f 100644 --- a/src/mainboard/asi/mb_5blmp/Config.lb +++ b/src/mainboard/asi/mb_5blmp/Config.lb @@ -138,9 +138,6 @@ chip northbridge/amd/gx1 # Northbridge # device pci 12.4 on # VGA (onboard) # chip drivers/pci/onboard # device pci 12.4 on end - # register "rom_address" = "0xfffc0000" # 256 KB image - # # register "rom_address" = "0xfff80000" # 512 KB image - # # register "rom_address" = "0xfff00000" # 1 MB image # end # end device pci 13.0 on end # USB diff --git a/src/mainboard/asi/mb_5blmp/devicetree.cb b/src/mainboard/asi/mb_5blmp/devicetree.cb index 8ec750cda6..0b1505a136 100644 --- a/src/mainboard/asi/mb_5blmp/devicetree.cb +++ b/src/mainboard/asi/mb_5blmp/devicetree.cb @@ -40,9 +40,6 @@ chip northbridge/amd/gx1 # Northbridge # device pci 12.4 on # VGA (onboard) # chip drivers/pci/onboard # device pci 12.4 on end - # register "rom_address" = "0xfffc0000" # 256 KB image - # # register "rom_address" = "0xfff80000" # 512 KB image - # # register "rom_address" = "0xfff00000" # 1 MB image # end # end device pci 13.0 on end # USB diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb index 4d51c9971e..e27f2d12cf 100644 --- a/src/mainboard/asus/mew-vm/Config.lb +++ b/src/mainboard/asus/mew-vm/Config.lb @@ -99,7 +99,6 @@ chip northbridge/intel/i82810 device pci 1.0 on # Onboard Video #chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" #end end chip southbridge/intel/i82801xx # Southbridge @@ -109,7 +108,6 @@ chip northbridge/intel/i82810 device pci 1e.0 on # PCI Bridge #chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" #end end device pci 1f.0 on # ISA/LPC? Bridge diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb index 5ff718604c..650aad1c42 100644 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ b/src/mainboard/asus/mew-vm/devicetree.cb @@ -4,7 +4,6 @@ chip northbridge/intel/i82810 device pci 1.0 on # Onboard Video #chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" #end end chip southbridge/intel/i82801xx # Southbridge @@ -14,7 +13,6 @@ chip northbridge/intel/i82810 device pci 1e.0 on # PCI Bridge #chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" #end end device pci 1f.0 on # ISA/LPC? Bridge diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb index e400b958e2..3b0d217437 100644 --- a/src/mainboard/broadcom/blast/Config.lb +++ b/src/mainboard/broadcom/blast/Config.lb @@ -211,7 +211,6 @@ chip northbridge/amd/amdk8/root_complex chip drivers/pci/onboard device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - register "rom_address" = "0xfff80000" end end #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) @@ -220,7 +219,6 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/pci/onboard # device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# register "rom_address" = "0xfff80000" # end diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index 4c35506332..b9dc91b720 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -109,7 +109,6 @@ chip northbridge/amd/amdk8/root_complex chip drivers/pci/onboard device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - register "rom_address" = "0xfff80000" end end #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) @@ -118,7 +117,6 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/pci/onboard # device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# register "rom_address" = "0xfff80000" # end diff --git a/src/mainboard/digitallogic/msm586seg/Config.lb b/src/mainboard/digitallogic/msm586seg/Config.lb index f223884883..ef8a0eb69c 100644 --- a/src/mainboard/digitallogic/msm586seg/Config.lb +++ b/src/mainboard/digitallogic/msm586seg/Config.lb @@ -108,7 +108,6 @@ chip cpu/amd/sc520 end chip drivers/pci/onboard device pci 14.0 on end # 69000 - register "rom_address" = "0x2000000" end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" diff --git a/src/mainboard/digitallogic/msm586seg/devicetree.cb b/src/mainboard/digitallogic/msm586seg/devicetree.cb index 30606b5b7e..35db84ed8b 100644 --- a/src/mainboard/digitallogic/msm586seg/devicetree.cb +++ b/src/mainboard/digitallogic/msm586seg/devicetree.cb @@ -7,7 +7,6 @@ chip cpu/amd/sc520 end chip drivers/pci/onboard device pci 14.0 on end # 69000 - register "rom_address" = "0x2000000" end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb index 17223bd430..b043e275b5 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb +++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb @@ -180,7 +180,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # AGP bridge chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - register "rom_address" = "0xfff80000" end end device pci 2.0 on # LPC diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb index b7cc72f293..5ab88f4a39 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb +++ b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb @@ -13,7 +13,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # AGP bridge chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - register "rom_address" = "0xfff80000" end end device pci 2.0 on # LPC diff --git a/src/mainboard/hp/e_vectra_p2706t/Config.lb b/src/mainboard/hp/e_vectra_p2706t/Config.lb index 0677bbb00c..535c30caa0 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Config.lb +++ b/src/mainboard/hp/e_vectra_p2706t/Config.lb @@ -78,7 +78,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb index e049c6b46d..a10dee89fc 100644 --- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb +++ b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb @@ -9,7 +9,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" diff --git a/src/mainboard/ibm/e326/Config.lb b/src/mainboard/ibm/e326/Config.lb index c21a315acd..39ba3e2fad 100644 --- a/src/mainboard/ibm/e326/Config.lb +++ b/src/mainboard/ibm/e326/Config.lb @@ -127,7 +127,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end chip drivers/pci/onboard device pci 5.0 on end # ATI Rage XL - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb index 11c57e87a3..2e634e0058 100644 --- a/src/mainboard/ibm/e326/devicetree.cb +++ b/src/mainboard/ibm/e326/devicetree.cb @@ -23,7 +23,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end chip drivers/pci/onboard device pci 5.0 on end # ATI Rage XL - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/intel/d945gclf/Config.lb b/src/mainboard/intel/d945gclf/Config.lb index 7e59a47810..d9eee75168 100644 --- a/src/mainboard/intel/d945gclf/Config.lb +++ b/src/mainboard/intel/d945gclf/Config.lb @@ -152,9 +152,6 @@ chip northbridge/intel/i945 device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - # register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index ea84556ea3..eeab074f56 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -30,9 +30,6 @@ chip northbridge/intel/i945 device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - # register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb index b6ea0e291d..fc55d57a23 100644 --- a/src/mainboard/iwill/dk8_htx/Config.lb +++ b/src/mainboard/iwill/dk8_htx/Config.lb @@ -234,7 +234,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end #chip drivers/pci/onboard # device pci 6.0 on end - # register "rom_address" = "0xfff80000" #end end device pci 1.0 on diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb index 0d02cc8b59..b1d0d79bf1 100644 --- a/src/mainboard/iwill/dk8_htx/devicetree.cb +++ b/src/mainboard/iwill/dk8_htx/devicetree.cb @@ -26,7 +26,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end #chip drivers/pci/onboard # device pci 6.0 on end - # register "rom_address" = "0xfff80000" #end end device pci 1.0 on diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb index eab88a9589..e89fc82c0e 100644 --- a/src/mainboard/kontron/986lcd-m/Config.lb +++ b/src/mainboard/kontron/986lcd-m/Config.lb @@ -155,9 +155,6 @@ chip northbridge/intel/i945 # device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 2a3615bf5d..8cd34b4f96 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -11,9 +11,6 @@ chip northbridge/intel/i945 device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller diff --git a/src/mainboard/kontron/kt690/Config.lb b/src/mainboard/kontron/kt690/Config.lb index f1b4215aa4..3a182b7ba9 100644 --- a/src/mainboard/kontron/kt690/Config.lb +++ b/src/mainboard/kontron/kt690/Config.lb @@ -134,7 +134,6 @@ config chip.h #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -158,7 +157,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -168,7 +166,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb index e26350ccda..5983bbafd9 100644 --- a/src/mainboard/kontron/kt690/devicetree.cb +++ b/src/mainboard/kontron/kt690/devicetree.cb @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -23,7 +22,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -33,7 +31,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" diff --git a/src/mainboard/mitac/6513wu/Config.lb b/src/mainboard/mitac/6513wu/Config.lb index c008f99a2b..9072349fc5 100644 --- a/src/mainboard/mitac/6513wu/Config.lb +++ b/src/mainboard/mitac/6513wu/Config.lb @@ -82,7 +82,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) chip drivers/pci/onboard device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" diff --git a/src/mainboard/mitac/6513wu/devicetree.cb b/src/mainboard/mitac/6513wu/devicetree.cb index 0731b2f2cd..b78dd3aab9 100644 --- a/src/mainboard/mitac/6513wu/devicetree.cb +++ b/src/mainboard/mitac/6513wu/devicetree.cb @@ -28,7 +28,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) chip drivers/pci/onboard device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" diff --git a/src/mainboard/msi/ms6178/Config.lb b/src/mainboard/msi/ms6178/Config.lb index d8cea81e89..5c6f9c06bc 100644 --- a/src/mainboard/msi/ms6178/Config.lb +++ b/src/mainboard/msi/ms6178/Config.lb @@ -77,7 +77,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb index ac56d65b61..1676ab5a9a 100644 --- a/src/mainboard/msi/ms6178/devicetree.cb +++ b/src/mainboard/msi/ms6178/devicetree.cb @@ -28,7 +28,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb index c02f260fe9..0af1b60c4c 100644 --- a/src/mainboard/msi/ms9185/Config.lb +++ b/src/mainboard/msi/ms9185/Config.lb @@ -211,7 +211,6 @@ chip northbridge/amd/amdk8/root_complex chip drivers/pci/onboard device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - register "rom_address" = "0xfff80000" end #bx_a013+ start #chip drivers/pci/onboard #SATA2 @@ -229,7 +228,6 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/pci/onboard # device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# register "rom_address" = "0xfff80000" # end end # device pci 18.0 diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb index 23f6c8747c..3f02199d69 100644 --- a/src/mainboard/msi/ms9185/devicetree.cb +++ b/src/mainboard/msi/ms9185/devicetree.cb @@ -77,7 +77,6 @@ chip northbridge/amd/amdk8/root_complex chip drivers/pci/onboard device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - register "rom_address" = "0xfff80000" end #bx_a013+ start #chip drivers/pci/onboard #SATA2 @@ -95,7 +94,6 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/pci/onboard # device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# register "rom_address" = "0xfff80000" # end end # device pci 18.0 diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb index c5a82d3ad4..c0c4ed10e6 100644 --- a/src/mainboard/msi/ms9282/Config.lb +++ b/src/mainboard/msi/ms9282/Config.lb @@ -280,7 +280,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on #P2P chip drivers/pci/onboard device pci 4.0 on end - register "rom_address" = "0xfff80000" end end # P2P device pci 7.0 on end # reserve diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb index 6fd476b10a..bf334408e8 100644 --- a/src/mainboard/msi/ms9282/devicetree.cb +++ b/src/mainboard/msi/ms9282/devicetree.cb @@ -139,7 +139,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on #P2P chip drivers/pci/onboard device pci 4.0 on end - register "rom_address" = "0xfff80000" end end # P2P device pci 7.0 on end # reserve diff --git a/src/mainboard/nec/powermate2000/Config.lb b/src/mainboard/nec/powermate2000/Config.lb index 02be04a21b..ff75437720 100644 --- a/src/mainboard/nec/powermate2000/Config.lb +++ b/src/mainboard/nec/powermate2000/Config.lb @@ -78,7 +78,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 1.0 off # Onboard video # chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" # end end chip southbridge/intel/i82801xx # Southbridge diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb index cbbc322a24..5af5986a5a 100644 --- a/src/mainboard/nec/powermate2000/devicetree.cb +++ b/src/mainboard/nec/powermate2000/devicetree.cb @@ -9,7 +9,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 1.0 off # Onboard video # chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" # end end chip southbridge/intel/i82801xx # Southbridge diff --git a/src/mainboard/rca/rm4100/Config.lb b/src/mainboard/rca/rm4100/Config.lb index 87d96df2e1..727077d6be 100644 --- a/src/mainboard/rca/rm4100/Config.lb +++ b/src/mainboard/rca/rm4100/Config.lb @@ -77,7 +77,6 @@ chip northbridge/intel/i82830 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb index 09d1e2b635..f67692d8df 100644 --- a/src/mainboard/rca/rm4100/devicetree.cb +++ b/src/mainboard/rca/rm4100/devicetree.cb @@ -3,7 +3,6 @@ chip northbridge/intel/i82830 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb index b9f14ea4c9..2bc901af10 100644 --- a/src/mainboard/supermicro/h8dme/Config.lb +++ b/src/mainboard/supermicro/h8dme/Config.lb @@ -256,8 +256,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb index 90491e45ed..6df22c4f44 100644 --- a/src/mainboard/supermicro/h8dme/devicetree.cb +++ b/src/mainboard/supermicro/h8dme/devicetree.cb @@ -94,8 +94,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb index a93c3051c3..76f8e70aa1 100644 --- a/src/mainboard/supermicro/h8dmr/Config.lb +++ b/src/mainboard/supermicro/h8dmr/Config.lb @@ -278,8 +278,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb index 9f5fd765bf..9a09f1cc49 100644 --- a/src/mainboard/supermicro/h8dmr/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr/devicetree.cb @@ -114,8 +114,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA diff --git a/src/mainboard/supermicro/h8dmr_fam10/Config.lb b/src/mainboard/supermicro/h8dmr_fam10/Config.lb index 945662d135..31341bd0e1 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Config.lb +++ b/src/mainboard/supermicro/h8dmr_fam10/Config.lb @@ -282,8 +282,6 @@ chip northbridge/amd/amdfam10/root_complex device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index 584f48abd6..35cf05235f 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -116,8 +116,6 @@ chip northbridge/amd/amdfam10/root_complex device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA diff --git a/src/mainboard/technexion/tim5690/Config.lb b/src/mainboard/technexion/tim5690/Config.lb index d46aa3ba61..d400a2d6c9 100644 --- a/src/mainboard/technexion/tim5690/Config.lb +++ b/src/mainboard/technexion/tim5690/Config.lb @@ -134,7 +134,6 @@ config chip.h #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -158,10 +157,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" #512KB - #register "rom_address" = "0xfff00000" #1024KB - #register "rom_address" = "0xffe00000" #2048KB - #register "rom_address" = "0xffc00000" #4096KB end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -171,10 +166,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" - #register "vga_rom_address" = "0xfff00000" - #register "vga_rom_address" = "0xffe00000" - #register "vga_rom_address" = "0xffc00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb index fb95aad887..8bd6fe1f9d 100644 --- a/src/mainboard/technexion/tim5690/devicetree.cb +++ b/src/mainboard/technexion/tim5690/devicetree.cb @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -23,10 +22,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" #512KB - #register "rom_address" = "0xfff00000" #1024KB - #register "rom_address" = "0xffe00000" #2048KB - #register "rom_address" = "0xffc00000" #4096KB end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -36,10 +31,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" - #register "vga_rom_address" = "0xfff00000" - #register "vga_rom_address" = "0xffe00000" - #register "vga_rom_address" = "0xffc00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" diff --git a/src/mainboard/technexion/tim8690/Config.lb b/src/mainboard/technexion/tim8690/Config.lb index e69d01df60..a40bf65b7d 100644 --- a/src/mainboard/technexion/tim8690/Config.lb +++ b/src/mainboard/technexion/tim8690/Config.lb @@ -134,7 +134,6 @@ config chip.h #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -158,7 +157,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -168,7 +166,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb index b47e615e2d..10de5c16c8 100644 --- a/src/mainboard/technexion/tim8690/devicetree.cb +++ b/src/mainboard/technexion/tim8690/devicetree.cb @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -23,7 +22,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -33,7 +31,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" diff --git a/src/mainboard/technologic/ts5300/Config.lb b/src/mainboard/technologic/ts5300/Config.lb index 9f9e341784..5b665f9ad7 100644 --- a/src/mainboard/technologic/ts5300/Config.lb +++ b/src/mainboard/technologic/ts5300/Config.lb @@ -109,7 +109,6 @@ chip cpu/amd/sc520 # end # chip drivers/pci/onboard # device pci 14.0 on end # 69000 -# register "rom_address" = "0x2000000" # end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" diff --git a/src/mainboard/technologic/ts5300/devicetree.cb b/src/mainboard/technologic/ts5300/devicetree.cb index 4e752516c7..5823155cdb 100644 --- a/src/mainboard/technologic/ts5300/devicetree.cb +++ b/src/mainboard/technologic/ts5300/devicetree.cb @@ -7,7 +7,6 @@ chip cpu/amd/sc520 # end # chip drivers/pci/onboard # device pci 14.0 on end # 69000 -# register "rom_address" = "0x2000000" # end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb index 00c913cfcc..8eaa606ac4 100644 --- a/src/mainboard/thomson/ip1000/Config.lb +++ b/src/mainboard/thomson/ip1000/Config.lb @@ -77,7 +77,6 @@ chip northbridge/intel/i82830 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb index c3e0e7f8fe..aa0f3f93da 100644 --- a/src/mainboard/thomson/ip1000/devicetree.cb +++ b/src/mainboard/thomson/ip1000/devicetree.cb @@ -3,7 +3,6 @@ chip northbridge/intel/i82830 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb index 19f637fd29..3eeb4319cb 100644 --- a/src/mainboard/tyan/s2850/Config.lb +++ b/src/mainboard/tyan/s2850/Config.lb @@ -121,7 +121,6 @@ chip northbridge/amd/amdk8/root_complex #chip drivers/ati/ragexl chip drivers/pci/onboard device pci b.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb index ebb4fe60f8..1f93df19d3 100644 --- a/src/mainboard/tyan/s2850/devicetree.cb +++ b/src/mainboard/tyan/s2850/devicetree.cb @@ -19,7 +19,6 @@ chip northbridge/amd/amdk8/root_complex #chip drivers/ati/ragexl chip drivers/pci/onboard device pci b.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb index 63ea6be2cb..f0d93d0b80 100644 --- a/src/mainboard/tyan/s2875/Config.lb +++ b/src/mainboard/tyan/s2875/Config.lb @@ -125,7 +125,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end chip drivers/pci/onboard device pci 5.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb index 1b4bb28c38..6c6bf69cfa 100644 --- a/src/mainboard/tyan/s2875/devicetree.cb +++ b/src/mainboard/tyan/s2875/devicetree.cb @@ -23,7 +23,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end chip drivers/pci/onboard device pci 5.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 692184b18e..76018b156d 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -140,7 +140,6 @@ chip northbridge/amd/amdk8/root_complex end chip drivers/pci/onboard device pci 6.0 on end #adti - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb index 9d1e44c974..8593fb3573 100644 --- a/src/mainboard/tyan/s2880/devicetree.cb +++ b/src/mainboard/tyan/s2880/devicetree.cb @@ -38,7 +38,6 @@ chip northbridge/amd/amdk8/root_complex end chip drivers/pci/onboard device pci 6.0 on end #adti - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb index 92f50f8eff..b959220f72 100644 --- a/src/mainboard/tyan/s2881/Config.lb +++ b/src/mainboard/tyan/s2881/Config.lb @@ -141,7 +141,6 @@ chip northbridge/amd/amdk8/root_complex end chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb index 57673a9bea..7f1453bfa3 100644 --- a/src/mainboard/tyan/s2881/devicetree.cb +++ b/src/mainboard/tyan/s2881/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/amd/amdk8/root_complex end chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index 34b2e82a74..e92ea84948 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -141,7 +141,6 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" end chip drivers/pci/onboard device pci 8.0 on end #intel 10/100 diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb index 3c18bb6fd2..d4200d158e 100644 --- a/src/mainboard/tyan/s2882/devicetree.cb +++ b/src/mainboard/tyan/s2882/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" end chip drivers/pci/onboard device pci 8.0 on end #intel 10/100 diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb index 799931c521..49ae429bf5 100644 --- a/src/mainboard/tyan/s2912_fam10/Config.lb +++ b/src/mainboard/tyan/s2912_fam10/Config.lb @@ -281,7 +281,6 @@ chip northbridge/amd/amdfam10/root_complex device pci 6.0 on chip drivers/pci/onboard device pci 4.0 on end - register "rom_address" = "0xfff00000" end end # PCI device pci 6.1 off end # AZA diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index d02b81c2fd..4bce6b3e89 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -114,7 +114,6 @@ chip northbridge/amd/amdfam10/root_complex device pci 6.0 on chip drivers/pci/onboard device pci 4.0 on end - register "rom_address" = "0xfff00000" end end # PCI device pci 6.1 off end # AZA diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index 1838733d7c..68efa3bba8 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -135,7 +135,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb index 7dec1bcd10..d1e424b697 100644 --- a/src/mainboard/tyan/s4880/devicetree.cb +++ b/src/mainboard/tyan/s4880/devicetree.cb @@ -38,7 +38,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index f28c752078..48b2597451 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -134,7 +134,6 @@ chip northbridge/amd/amdk8/root_complex #chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end chip drivers/pci/onboard device pci 5.0 on end #SiI diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb index 1524a845c1..d61865cdd5 100644 --- a/src/mainboard/tyan/s4882/devicetree.cb +++ b/src/mainboard/tyan/s4882/devicetree.cb @@ -37,7 +37,6 @@ chip northbridge/amd/amdk8/root_complex #chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end chip drivers/pci/onboard device pci 5.0 on end #SiI diff --git a/src/mainboard/via/vt8454c/Config.lb b/src/mainboard/via/vt8454c/Config.lb index f685ddd3e4..3dd107ac52 100644 --- a/src/mainboard/via/vt8454c/Config.lb +++ b/src/mainboard/via/vt8454c/Config.lb @@ -123,9 +123,6 @@ chip northbridge/via/cx700 device pci 1.0 on # PCI Bridge chip drivers/pci/onboard device pci 0.0 on end - #register "rom_address" = "0xfffc0000" #256k image - register "rom_address" = "0xfff80000" #512k image - #register "rom_address" = "0xfff00000" #1024k image end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA diff --git a/src/mainboard/via/vt8454c/devicetree.cb b/src/mainboard/via/vt8454c/devicetree.cb index 02f9514984..3ef59b52e1 100644 --- a/src/mainboard/via/vt8454c/devicetree.cb +++ b/src/mainboard/via/vt8454c/devicetree.cb @@ -14,9 +14,6 @@ chip northbridge/via/cx700 device pci 1.0 on # PCI Bridge chip drivers/pci/onboard device pci 0.0 on end - #register "rom_address" = "0xfffc0000" #256k image - register "rom_address" = "0xfff80000" #512k image - #register "rom_address" = "0xfff00000" #1024k image end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA diff --git a/src/southbridge/amd/rs690/chip.h b/src/southbridge/amd/rs690/chip.h index 176b744fe0..6ae3dd5a0f 100644 --- a/src/southbridge/amd/rs690/chip.h +++ b/src/southbridge/amd/rs690/chip.h @@ -23,7 +23,6 @@ /* Member variables are defined in Config.lb. */ struct southbridge_amd_rs690_config { - u32 vga_rom_address; /* The location that the VGA rom has been appened. */ u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */ |