diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-20 21:25:07 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-06 12:12:43 +0000 |
| commit | 8b42a24d036fb6f5fc15a25f8d3d25f6fe6bd060 (patch) | |
| tree | c852984e2fc38ea03bba2dde25418825e03dccc1 | |
| parent | c5d71dc7ff9bc253a9151d1da9f55b0c59406820 (diff) | |
soc/amd/cezanne: remove LIDS field from global NVS
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Cezanne SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/mainboard/google/guybrush/dsdt.asl | 3 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/acpi/globalnvs.asl | 7 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/nvs.h | 7 |
3 files changed, 9 insertions, 8 deletions
diff --git a/src/mainboard/google/guybrush/dsdt.asl b/src/mainboard/google/guybrush/dsdt.asl index 6c208cf6c6..782bd9d4d7 100644 --- a/src/mainboard/google/guybrush/dsdt.asl +++ b/src/mainboard/google/guybrush/dsdt.asl @@ -13,6 +13,9 @@ DefinitionBlock ( ) { #include <acpi/dsdt_top.asl> + + Name(LIDS, 0) + #include <soc.asl> /* ChromeOS Embedded Controller */ diff --git a/src/soc/amd/cezanne/acpi/globalnvs.asl b/src/soc/amd/cezanne/acpi/globalnvs.asl index bccce09678..f4a6c5f69b 100644 --- a/src/soc/amd/cezanne/acpi/globalnvs.asl +++ b/src/soc/amd/cezanne/acpi/globalnvs.asl @@ -8,8 +8,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - LIDS, 8, // 0x00 - LID State - CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console - PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index - GPEI, 64, // 0x0d - 0x14 - GPE Wake Source + CBMC, 32, // 0x00 - 0x03 - coreboot Memory Console + PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index + GPEI, 64, // 0x0c - 0x13 - GPE Wake Source } diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h index d990f45773..d1a8e3058f 100644 --- a/src/soc/amd/cezanne/include/soc/nvs.h +++ b/src/soc/amd/cezanne/include/soc/nvs.h @@ -13,10 +13,9 @@ struct __packed global_nvs { /* Miscellaneous */ - uint8_t lids; /* 0x00 - LID State */ - uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */ - uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */ + uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ + uint64_t pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0c - 0x13 - GPE Wake Source */ }; #endif /* AMD_CEZANNE_NVS_H */ |