diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-01 11:21:53 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-10 18:19:58 +0200 |
| commit | 35a7249183d2e791eb00b41332e6277c504cdd49 (patch) | |
| tree | ca73ef3d75e19dafad5fdea0cce1abcfdcd7d234 | |
| parent | 25dd2479c1890d45935d7dbfc14599385e1893dd (diff) | |
intel/gm45: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO for all boards
with gm45 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.
Change-Id: Id1c839b7d669946e0ca8b6837e5152ebcb9cd334
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3600
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
| -rw-r--r-- | src/northbridge/intel/gm45/Kconfig | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/bootblock.c | 27 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/early_init.c | 5 |
3 files changed, 31 insertions, 5 deletions
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 16a0bf175e..adf1c1b356 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,4 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select IOMMU +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/gm45/bootblock.c" + endif diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c new file mode 100644 index 0000000000..fb40b9446a --- /dev/null +++ b/src/northbridge/intel/gm45/bootblock.c @@ -0,0 +1,27 @@ +#include <arch/io.h> + +/* Just re-define these instead of including gm45.h. It blows up romcc. */ +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); +} diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 052c517781..ed5bf99210 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -25,11 +25,6 @@ void gm45_early_init(void) { const device_t d0f0 = PCI_DEV(0, 0, 0); - /* Setup PCIEXBAR. */ - pci_io_write_config32(d0f0, D0F0_PCIEXBAR_LO, - /* 64MB, enable */ - DEFAULT_PCIEXBAR | (2 << 1) | 1); - /* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1); |