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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2021-09-11 09:46:18 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-09-16 21:00:26 +0000
commit215ff5d9500803703399e3bc7de9883de55fd03c (patch)
treef0e935ca515289d0ccca44325cfcfc4f4410a2bc
parenta398be98313246866a14f9a0af5e56bae233aaf9 (diff)
mb/google/brya/variants/kano: Add MIPI camera support
Add MIPI camera support for OVTI2740 BUG=b:196937374 b:194926283 TEST=Build and boot on Kano Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I248c64b9460c898f9faa5f7ac8cf339a9c814013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/mainboard/google/brya/Kconfig.name2
-rw-r--r--src/mainboard/google/brya/variants/kano/overridetree.cb67
2 files changed, 68 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index be0d77f68e..d2171d5857 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -43,6 +43,8 @@ config BOARD_GOOGLE_KANO
select DRIVERS_I2C_MAX98373
select DRIVERS_I2C_NAU8825
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+ select DRIVERS_INTEL_MIPI_CAMERA
+ select SOC_INTEL_COMMON_BLOCK_IPU
config BOARD_GOOGLE_TAEKO
bool "-> Taeko"
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index ac565cce2c..5fc0c6b3a6 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -103,7 +103,19 @@ chip soc/intel/alderlake
device generic 0 on end
end
end
- device ref ipu on end
+ device ref ipu on
+ chip drivers/intel/mipi_camera
+ register "acpi_uid" = "0x50000"
+ register "acpi_name" = ""IPU0""
+ register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+ register "cio2_num_ports" = "1"
+ register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
+ register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
+ register "cio2_prt[0]" = "2"
+ device generic 0 on end
+ end
+ end
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{
@@ -275,6 +287,59 @@ chip soc/intel/alderlake
register "reg_adv_ctrl20" = "0xf0"
device i2c 2C on end
end
+ chip drivers/intel/mipi_camera
+ register "acpi_hid" = ""OVTI2740""
+ register "acpi_uid" = "0"
+ register "acpi_name" = ""CAM0""
+ register "chip_name" = ""Ov 2740 Camera""
+ register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+ register "has_power_resource" = "1"
+
+ register "ssdb.lanes_used" = "2"
+ register "ssdb.link_used" = "1"
+ register "num_freq_entries" = "1"
+ register "link_freq[0]" = "DEFAULT_LINK_FREQ"
+ register "remote_name" = ""IPU0""
+
+ #Controls
+ register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+ register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_F20" #reset
+ register "gpio_panel.gpio[1].gpio_num" = "GPP_C4" #power
+
+ #_ON
+ register "on_seq.ops_cnt" = "4"
+ register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+ register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+ register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "3"
+ register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+ register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+
+ device i2c 36 on end
+ end
+ chip drivers/intel/mipi_camera
+ register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+ register "acpi_uid" = "1"
+ register "acpi_name" = ""NVM0""
+ register "chip_name" = ""AT24 EEPROM""
+ register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+ register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC""
+
+ register "nvm_size" = "0x2000"
+ register "nvm_pagesize" = "1"
+ register "nvm_readonly" = "1"
+ register "nvm_width" = "0x10"
+ register "nvm_compat" = ""atmel,24c64""
+
+ device i2c 50 on end
+ end
end
device ref i2c3 on end
device ref i2c5 on