diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 10:04:56 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-12-01 10:28:10 +0000 |
| commit | 1eecb8c814fa05e9902ddcb139a6e8b3a226ffa6 (patch) | |
| tree | 5897829e5767fcf0d7f27c51b355b9027c2e64c8 | |
| parent | 22d6ee8d9cda51d20ca4173593b9574f7dac65ff (diff) | |
nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
19 files changed, 74 insertions, 48 deletions
diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index a713f34f70..713ac40d2f 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x8086 0x0028 inherit device pci 0.0 on end # Host Bridge device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index ff0503066c..5d10628a62 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 89e6ebb8fc..d0759e2346 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index c3c6b1b17a..818ceaa5c0 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 9d22761a7c..9f4142bf5d 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 8693c0196d..e0df76be96 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb index 9057ed7daa..c452672d92 100644 --- a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 6.0 off end # PEG 2 diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index bc9dff630d..b0452d4d57 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 off end # Integrated graphics controller diff --git a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb index 01de13fa67..8390bc0f92 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 off end # Integrated graphics controller diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 1b50903842..70e82e84e8 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 off end # Integrated graphics controller diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 01de13fa67..8390bc0f92 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 off end # Integrated graphics controller diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index 242ea5a0d8..a839b9dda1 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on # Host Bridge subsystemid 0x1043 0x8336 end diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 1cbee74009..82b1c61078 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 9bde4b2b9c..578f13d805 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -1,7 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc64a4..d2168630ba 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1458 0x5000 diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 5f945c1c33..9e5c136bc2 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x8086 0x5756 diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index bb2456f537..5e2eb9d60b 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xacac off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x8086 0x0028 inherit device pci 0.0 on end # Host Bridge device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index e5d10d7ac6..a4b9ac8e9f 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x17aa 0x304f inherit device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index ac276b69d4..da046d1697 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -144,7 +144,7 @@ void northbridge_write_smram(u8 smram) pci_write_config8(dev, D0F0_SMRAM, smram); } -static struct device_operations pci_domain_ops = { +struct device_operations x4x_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, @@ -154,21 +154,12 @@ static struct device_operations pci_domain_ops = { .acpi_name = northbridge_acpi_name, }; -static struct device_operations cpu_bus_ops = { +struct device_operations x4x_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) - dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) - dev->ops = &cpu_bus_ops; -} - static void hide_pci_fn(const int dev_bit_base, const struct device *dev) { if (!dev || dev->enabled) @@ -201,6 +192,5 @@ static void x4x_init(void *const chip_info) struct chip_operations northbridge_intel_x4x_ops = { CHIP_NAME("Intel 4-Series Northbridge") - .enable_dev = enable_dev, .init = x4x_init, }; |