src/soc/intel: Add Cometlake-S and CMP-H skus

This patch adds some sku support for CML-S CPU and CMP-H chips.
According to doc #605546:
CML-S (6+2) G0: A0650h
CML-S (6+2) G1: A0653h
CML-S (10+2, 8+2) P0: A0651h
CML-S (6+2, 10+2) Q0/P1: A0654h

CMP-H HM470: 068Dh
CMP-H WM490: 068Eh
CMP-H QM480: 068Ch
CMP-H H470: 0684h
CMP-H Z490: 0685h
CMP-H Q470: 0687h

TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized

Change-Id: I6bda09070ec330033eff95329448ace57e87144f
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

6 files changed, 48 insertions, 7 deletions

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 0f96737f3b..b75e596d19 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2769,6 +2769,14 @@
 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC	0x0284
 #define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC	0x0285
 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC	0x0286
+#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470	0x068D
+#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490	0x068E
+#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480	0x068C
+#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480	0x0697
+#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470	0x0684
+#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490	0x0685
+#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470	0x0687
+#define PCI_DEVICE_ID_INTEL_TGL_ESPI		0xA083
 #define PCI_DEVICE_ID_INTEL_TGP_ESPI_0	0xA080
 #define PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI	0xA081
 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI	0xA082
@@ -3262,6 +3270,14 @@
 #define PCI_DEVICE_ID_INTEL_CML_GT1_H_2			0x9B22
 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_1			0x9B44
 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2			0x9B42
+#define PCI_DEVICE_ID_INTEL_CML_GT2_S_G0		0x9BC8
+#define PCI_DEVICE_ID_INTEL_CML_GT2_S_P0		0x9BC5
+#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R0		0x3E9B
+#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R1		0x9BC4
+#define PCI_DEVICE_ID_INTEL_TGL_GT1                     0X9A60
+#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY                  0X9A49
+#define PCI_DEVICE_ID_INTEL_TGL_GT2                     0XFF20
+#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y                   0X9A40
 #define PCI_DEVICE_ID_INTEL_TGL_GT0			0x9A7F
 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT			0x9A49
 #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT			0x9A52
@@ -3313,7 +3329,9 @@
 #define PCI_DEVICE_ID_INTEL_CML_ULT_6_2		0x9B51
 #define PCI_DEVICE_ID_INTEL_CML_ULX		0x9B60
 #define PCI_DEVICE_ID_INTEL_CML_S		0x9B55
-#define PCI_DEVICE_ID_INTEL_CML_S_10_2		0x9B35
+#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2	0x9B53
+#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2	0x9B35
+#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2	0x9B43
 #define PCI_DEVICE_ID_INTEL_CML_H		0x9B54
 #define PCI_DEVICE_ID_INTEL_CML_H_8_2		0x9B44
 #define PCI_DEVICE_ID_INTEL_TGL_ID_U		0x9A14
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index 3d46916133..8d823850fd 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -45,8 +45,10 @@ static struct {
 	{ CPUID_COFFEELAKE_R0, "Coffeelake R0" },
 	{ CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" },
 	{ CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" },
-	{ CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" },
+	{ CPUID_COMETLAKE_H_S_6_2_G0, "Cometlake-H/S G0 (6+2)" },
+	{ CPUID_COMETLAKE_H_S_6_2_G1, "Cometlake-H/S G1 (6+2)" },
 	{ CPUID_COMETLAKE_H_S_10_2_P0, "Cometlake-H/S P0 (10+2)" },
+	{ CPUID_COMETLAKE_H_S_10_2_Q0_P1, "Cometlake-H/S Q0/P1 (10+2)" },
 };
 
 static struct {
@@ -77,7 +79,9 @@ static struct {
 	{ PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" },
 	{ PCI_DEVICE_ID_INTEL_CML_ULX, "CometLake-ULX (4+2)" },
 	{ PCI_DEVICE_ID_INTEL_CML_S, "CometLake-S (6+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_S_10_2, "CometLake-S (10+2)" },
+	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" },
+	{ PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" },
+	{ PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" },
 	{ PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" },
 	{ PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" },
 };
@@ -104,6 +108,13 @@ static struct {
 	{ PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" },
 	{ PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, "Cometlake-U Base" },
 	{ PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, "Cometlake-Y Super" },
+	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470, "Cometlake-H HM470" },
+	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490, "Cometlake-H WM490" },
+	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480, "Cometlake-H QM480" },
+	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480, "Cometlake-H W480" },
+	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470, "Cometlake-H H470" },
+	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490, "Cometlake-H Z490" },
+	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470, "Cometlake-H Q470" },
 };
 
 static struct {
@@ -143,10 +154,15 @@ static struct {
 	{ PCI_DEVICE_ID_INTEL_CML_GT1_S_2, "CometLake S GT1" },
 	{ PCI_DEVICE_ID_INTEL_CML_GT2_S_1, "CometLake S GT2" },
 	{ PCI_DEVICE_ID_INTEL_CML_GT2_S_2, "CometLake S GT2" },
+	{ PCI_DEVICE_ID_INTEL_CML_GT2_S_G0, "CometLake S GT2 G0" },
+	{ PCI_DEVICE_ID_INTEL_CML_GT2_S_P0, "CometLake S GT2 P0" },
 	{ PCI_DEVICE_ID_INTEL_CML_GT1_H_1, "CometLake H GT1" },
 	{ PCI_DEVICE_ID_INTEL_CML_GT1_H_2, "CometLake H GT1" },
 	{ PCI_DEVICE_ID_INTEL_CML_GT2_H_1, "CometLake H GT2" },
 	{ PCI_DEVICE_ID_INTEL_CML_GT2_H_2, "CometLake H GT2" },
+	{ PCI_DEVICE_ID_INTEL_CML_GT2_H_R0, "CometLake H GT2 R0" },
+	{ PCI_DEVICE_ID_INTEL_CML_GT2_H_R1, "CometLake H GT2 R1" },
+
 };
 
 static uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index a7fcd94d67..c4eb884a75 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -83,7 +83,8 @@ uint8_t get_pch_series(void)
 	case 0x02: /* CML-LP */
 		pch_series = PCH_LP;
 		break;
-	case 0xA3:
+	case 0xA3: /* CFL-H */
+	case 0x06: /* CML-H */
 		pch_series = PCH_H;
 		break;
 	default:
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index df571ba775..721e42c03c 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -82,8 +82,10 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_ICELAKE_B0 },
 	{ X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 },
 	{ X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0 },
-	{ X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_P0 },
+	{ X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G0 },
+	{ X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G1 },
 	{ X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 },
+	{ X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 },
 	{ X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 },
 	{ 0, 0 },
 };
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index e5475383f7..aaf1793a14 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -49,8 +49,10 @@
 #define CPUID_ICELAKE_B0	0x706e1
 #define CPUID_COMETLAKE_U_A0		0xa0660
 #define CPUID_COMETLAKE_U_K0_S0		0xa0661
-#define CPUID_COMETLAKE_H_S_6_2_P0	0xa0650
+#define CPUID_COMETLAKE_H_S_6_2_G0	0xa0650
+#define CPUID_COMETLAKE_H_S_6_2_G1	0xa0653
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
+#define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
 #define CPUID_TIGERLAKE_A0	0x806c0
 
 /*
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 5f7d5af82c..b3657069f1 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -359,7 +359,9 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DEVICE_ID_INTEL_CML_ULT_6_2,
 	PCI_DEVICE_ID_INTEL_CML_ULX,
 	PCI_DEVICE_ID_INTEL_CML_S,
-	PCI_DEVICE_ID_INTEL_CML_S_10_2,
+	PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2,
+	PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2,
+	PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2,
 	PCI_DEVICE_ID_INTEL_CML_H,
 	PCI_DEVICE_ID_INTEL_CML_H_8_2,
 	PCI_DEVICE_ID_INTEL_TGL_ID_U,