diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-11-30 14:53:00 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-04 21:10:31 +0000 |
| commit | ce66f34372bb9dcda107bae983d38da25a5664d1 (patch) | |
| tree | 1a4725fe0f7adf562b2d7875e175c3546c6b3e4d | |
| parent | ff6a1e5149e0b32ce7141d0354598d81166628f0 (diff) | |
mb/google/brya: Initiate device tree
Initiate device tree based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index fbd7d72f9f..479a7eeb19 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -2,4 +2,41 @@ chip soc/intel/alderlake device cpu_cluster 0 on device lapic 0 on end end + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tcss_xhci on end + device ref tcss_dma0 on end + device ref tcss_dma1 on end + device ref cnvi_bt on end + device ref xhci on end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end #USB3-1 Type A + device ref pcie_rp4 on end #USB3-4 WWAN + device ref pcie_rp5 on end #PCIE5 WLAN + device ref pcie_rp6 on end #PCIE6 WWAN + device ref pcie_rp8 on end #PCIE8 SD card + device ref pcie_rp9 on end #PCIE9-12 SSD + device ref uart0 on end + device ref gspi0 on end + device ref gspi1 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref hda on end + end end |