mb/google/sarien: Add Arcada variant

Add a variant of the Sarien board called Arcada.  This is currently
very similar to Sarien with differences in PCIe, USB, and GPIO usage.

Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29410
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 488 insertions, 0 deletions

diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index 4bf5191270..ac1afd5e27 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -30,6 +30,7 @@ config CHROMEOS
 
 config DEVICETREE
 	string
+	default "variants/arcada/devicetree.cb" if BOARD_GOOGLE_ARCADA
 	default "variants/sarien/devicetree.cb" if BOARD_GOOGLE_SARIEN
 
 config DIMM_MAX
@@ -55,6 +56,7 @@ config TPM_TIS_ACPI_INTERRUPT
 config GBB_HWID
 	string
 	depends on CHROMEOS
+	default "ARCADA TEST 3556" if BOARD_GOOGLE_ARCADA
 	default "SARIEN TEST 2787" if BOARD_GOOGLE_SARIEN
 
 config MAINBOARD_DIR
@@ -63,10 +65,12 @@ config MAINBOARD_DIR
 
 config MAINBOARD_FAMILY
 	string
+	default "Google_Arcada" if BOARD_GOOGLE_ARCADA
 	default "Google_Sarien" if BOARD_GOOGLE_SARIEN
 
 config MAINBOARD_PART_NUMBER
 	string
+	default "Arcada" if BOARD_GOOGLE_ARCADA
 	default "Sarien" if BOARD_GOOGLE_SARIEN
 
 config MAINBOARD_VENDOR
@@ -79,6 +83,7 @@ config MAX_CPUS
 
 config VARIANT_DIR
 	string
+	default "arcada" if BOARD_GOOGLE_ARCADA
 	default "sarien" if BOARD_GOOGLE_SARIEN
 
 config VBOOT
diff --git a/src/mainboard/google/sarien/Kconfig.name b/src/mainboard/google/sarien/Kconfig.name
index dcf279b4ce..77446e1aab 100644
--- a/src/mainboard/google/sarien/Kconfig.name
+++ b/src/mainboard/google/sarien/Kconfig.name
@@ -1,5 +1,9 @@
 comment "Sarien"
 
+config BOARD_GOOGLE_ARCADA
+	bool "->  Arcada"
+	select BOARD_GOOGLE_BASEBOARD_SARIEN
+
 config BOARD_GOOGLE_SARIEN
 	bool "->  Sarien"
 	select BOARD_GOOGLE_BASEBOARD_SARIEN
diff --git a/src/mainboard/google/sarien/variants/arcada/Makefile.inc b/src/mainboard/google/sarien/variants/arcada/Makefile.inc
new file mode 100644
index 0000000000..2bf028eb1f
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/arcada/Makefile.inc
@@ -0,0 +1,19 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2018 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+ramstage-y += gpio.c
+romstage-y += gpio.c
+verstage-y += gpio.c
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
new file mode 100644
index 0000000000..939acd2625
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -0,0 +1,163 @@
+chip soc/intel/cannonlake
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "PMC_GPP_A"
+	register "gpe0_dw1" = "PMC_GPP_C"
+	register "gpe0_dw2" = "PMC_GPP_D"
+
+	# FSP configuration
+	register "SaGv" = "3"
+	register "HeciEnabled" = "1"
+	register "SataSalpSupport" = "1"
+	register "SataMode" = "0"
+	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsEnable[2]" = "1"
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "1"
+	register "SataPortsDevSlp[2]" = "1"
+	register "InternalGfx" = "1"
+	register "SkipExtGfxScan" = "1"
+	register "VmxEnable" = "1"
+
+	register "speed_shift_enable" = "1"
+	register "s0ix_enable" = "1"
+
+	# Intel Common SoC Config
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C
+	register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)"	# Ext USB2 Port 3
+	register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)"	# Ext USB2 Port 4
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# USH
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# FPR in PB
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 2230 (BT)
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# Ext USB3 Port 3
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"	# Ext USB3 Port 4
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 3042 (WWAN)
+	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
+	#| I2C0              | Touchscreen               |
+	#| I2C1              | Touchpad                  |
+	#| I2C4              | H1 TPM                    |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[4] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	# PCIe port 9 for LAN
+	register "PcieRpEnable[8]" = "1"
+	register "PcieClkSrcUsage[0]" = "8"
+	register "PcieClkSrcClkReq[0]" = "0"
+
+	# PCIe port 10 for M.2 2230 WLAN
+	register "PcieRpEnable[9]" = "1"
+	register "PcieClkSrcUsage[2]" = "9"
+	register "PcieClkSrcClkReq[2]" = "2"
+
+	# PCIe port 11 for card reader
+	register "PcieRpEnable[10]" = "1"
+	register "PcieClkSrcUsage[1]" = "10"
+	register "PcieClkSrcClkReq[1]" = "1"
+
+	# PCIe port 12 for M.2 3042
+	register "PcieRpEnable[11]" = "1"
+	register "PcieClkSrcUsage[3]" = "11"
+	register "PcieClkSrcClkReq[3]" = "3"
+
+	# PCIe port 13 for M.2 2280 SSD
+	register "PcieRpEnable[12]" = "1"
+	register "PcieClkSrcUsage[4]" = "12"
+	register "PcieClkSrcClkReq[4]" = "4"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ACPI0C50""
+				register "generic.desc" = ""Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)"
+				device i2c 50 on end
+			end
+		end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1c.0 off end # PCI Express Port 1 (USB)
+		device pci 1c.1 off end # PCI Express Port 2 (USB)
+		device pci 1c.2 off end # PCI Express Port 3 (USB)
+		device pci 1c.3 off end # PCI Express Port 4 (USB)
+		device pci 1c.4 off end # PCI Express Port 5 (USB)
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 on  end # PCI Express Port 10
+		device pci 1d.2 on  end # PCI Express Port 11
+		device pci 1d.3 on  end # PCI Express Port 12
+		device pci 1d.4 on  end # PCI Express Port 13 (x4)
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on  end # LPC/eSPI
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 on  end # GbE
+	end
+end
diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
new file mode 100644
index 0000000000..86da3ec97f
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -0,0 +1,263 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+/* RCIN# */		PAD_NC(GPP_A0, NONE),
+/* ESPI_IO0 */
+/* ESPI_IO1 */
+/* ESPI_IO2 */
+/* ESPI_IO3 */
+/* ESPI_CS# */
+/* SERIRQ */
+/* PIRQA# */		PAD_NC(GPP_A7, NONE),
+/* CLKRUN# */		PAD_NC(GPP_A8, NONE),
+/* ESPI_CLK */
+/* CLKOUT_LPC1 */	PAD_NC(GPP_A10, NONE),
+/* PME# */		PAD_NC(GPP_A11, NONE),
+/* BM_BUSY# */		PAD_NC(GPP_A12, NONE),
+/* SUSWARN# */		PAD_NC(GPP_A13, NONE),
+/* ESPI_RESET# */
+/* SUSACK# */		PAD_NC(GPP_A15, NONE),
+/* SD_1P8_SEL */	PAD_NC(GPP_A16, NONE),
+/* SD_PWR_EN# */	PAD_NC(GPP_A17, NONE),
+/* ISH_GP0 */		PAD_NC(GPP_A18, NONE),
+/* ISH_GP1 */		PAD_NC(GPP_A19, NONE),
+/* ISH_GP2 */		PAD_NC(GPP_A20, NONE),
+/* ISH_GP3 */		PAD_NC(GPP_A21, NONE),
+/* ISH_GP4 */		PAD_NC(GPP_A22, NONE),
+/* ISH_GP5 */		PAD_NC(GPP_A23, NONE),
+
+/* CORE_VID0 */
+/* CORE_VID1 */
+/* VRALERT# */		PAD_NC(GPP_B2, NONE),
+/* CPU_GP2 */		PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP,
+				 EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
+/* CPU_GP3 */		PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
+/* SRCCLKREQ0# */	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+/* SRCCLKREQ1# */	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+/* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+/* SRCCLKREQ3# */	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+/* SRCCLKREQ4# */	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+/* SRCCLKREQ5# */	PAD_NC(GPP_B10, NONE),
+/* EXT_PWR_GATE# */	PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
+/* SLP_S0# */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PLTRST# */		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* SPKR */		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+/* GSPI0_CS# */		PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */
+/* GSPI0_CLK */		PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */
+/* GSPI0_MISO */	PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */
+/* GSPI0_MOSI */	PAD_NC(GPP_B18, NONE),
+/* GSPI1_CS# */		PAD_NC(GPP_B19, NONE),
+/* GSPI1_CLK */		PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
+/* GSPI1_MISO */	PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
+/* GSPI1_MOSI */	PAD_NC(GPP_B22, NONE),
+/* SML1ALERT# */	PAD_NC(GPP_B23, DN_20K),
+
+/* SMBCLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */
+/* SMBDATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */
+/* SMBALERT# */		PAD_NC(GPP_C2, DN_20K),
+/* SML0CLK */		PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */
+/* SML0DATA */		PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */
+/* SML0ALERT# */	PAD_NC(GPP_C5, DN_20K),
+/* SM1CLK */		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */
+/* SM1DATA */		PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */
+/* UART0_RXD */		PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */
+/* UART0_TXD */		PAD_NC(GPP_C9, NONE),
+/* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */
+/* UART0_CTS# */	PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */
+/* UART1_RXD */         PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
+				    EDGE_SINGLE), /* SIO_EXT_WAKE# */
+/* UART1_TXD */		PAD_NC(GPP_C13, NONE),
+/* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */
+/* UART1_CTS# */	PAD_NC(GPP_C15, NONE),
+/* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */
+/* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */
+/* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */
+/* I2C1_SCL */		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */
+/* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
+/* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
+/* UART2_RTS# */	PAD_NC(GPP_C22, NONE),
+/* UART2_CTS# */	PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP,
+				 EDGE_SINGLE, INVERT), /* TS_INT# */
+
+/* SPI1_CS# */		PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP,
+				 EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
+/* SPI1_CLK */		PAD_NC(GPP_D1, NONE),
+/* SPI1_MISO */		PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */
+/* SPI1_MOSI */		PAD_NC(GPP_D3, NONE),
+/* FASHTRIG */		PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */
+			/* ISH_I2C0_ACC_SDA */
+/* ISH_I2C0_SDA */	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+			/* ISH_I2C0_ACC_SCL */
+/* ISH_I2C0_SCL */	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+/* ISH_I2C1_SDA */	PAD_NC(GPP_D7, NONE),
+/* ISH_I2C1_SCL */	PAD_NC(GPP_D8, NONE),
+/* ISH_SPI_CS# */	PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */
+/* ISH_SPI_CLK */	PAD_NC(GPP_D10, NONE),
+/* ISH_SPI_MISO */	PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */
+/* ISH_SPI_MOSI */	PAD_NC(GPP_D12, NONE),
+/* ISH_UART0_RXD */	PAD_NC(GPP_D13, NONE),
+/* ISH_UART0_TXD */	PAD_NC(GPP_D14, NONE),
+/* ISH_UART0_RTS# */	PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
+/* ISH_UART0_CTS# */	PAD_NC(GPP_D16, NONE),
+/* DMIC_CLK1 */		PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
+/* DMIC_DATA1 */	PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
+				 EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
+/* DMIC_CLK0 */		PAD_NC(GPP_D19, NONE),
+/* DMIC_DATA0 */	PAD_NC(GPP_D20, NONE),
+/* SPI1_IO2 */		PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */
+/* SPI1_IO3 */		PAD_CFG_GPO(GPP_D22, 1, DEEP), /* WWAN_GPIO_PERST# */
+/* I2S_MCLK */		PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP,
+				 EDGE_SINGLE), /* WWAN_GPIO_WAKE# */
+
+/* SATAXPCIE0 */	PAD_NC(GPP_E0, NONE),
+			/* M3042_PCIE#_SATA */
+/* SATAXPCIE1 */	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+			/* M2880_PCIE_SATA# */
+/* SATAXPCIE2 */	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
+/* CPU_GP0 */		PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
+/* SATA_DEVSLP0 */	PAD_NC(GPP_E4, NONE),
+/* SATA_DEVSLP1 */	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */
+/* SATA_DEVSLP2 */	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */
+/* CPU_GP1 */		PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */
+/* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
+/* USB2_OCO# */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */
+/* USB2_OC1# */		PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */
+/* USB2_OC2# */		PAD_NC(GPP_E11, NONE),
+/* USB2_OC3# */		PAD_NC(GPP_E12, NONE),
+/* DDPB_HPD0 */		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */
+/* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */
+/* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
+/* DDPE_HPD3 */		PAD_NC(GPP_E16, NONE),
+/* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+/* DDPC_CTRLCLK */	PAD_NC(GPP_E20, NONE),
+/* DDPC_CTRLDATA */	PAD_NC(GPP_E21, NONE),
+/* DDPD_CTRLCLK */	PAD_NC(GPP_E22, NONE),
+/* DDPD_CTRLDATA */	PAD_NC(GPP_E23, NONE),
+
+/* CNV_PA_BLANKING */	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */
+/* GPP_F1 */		PAD_NC(GPP_F1, NONE),
+/* GPP_F2 */		PAD_NC(GPP_F2, NONE),
+/* GPP_F3 */		PAD_NC(GPP_F3, NONE),
+/* CNV_BRI_DT */	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+/* CNV_BRI_RSP */	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+/* CNV_RGI_DT */	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+/* CNV_RGI_RSP */	PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
+/* CNV_MFUART2_RXD */	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */
+/* CNV_MFUART2_TXD */	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */
+/* GPP_F10 */		PAD_NC(GPP_F10, NONE),
+/* EMMC_CMD */		PAD_NC(GPP_F11, NONE),
+/* EMMC_DATA0 */	PAD_NC(GPP_F12, NONE),
+/* EMMC_DATA1 */	PAD_NC(GPP_F13, NONE),
+/* EMMC_DATA2 */	PAD_NC(GPP_F14, NONE),
+/* EMMC_DATA3 */	PAD_NC(GPP_F15, NONE),
+/* EMMC_DATA4 */	PAD_NC(GPP_F16, NONE),
+/* EMMC_DATA5 */	PAD_NC(GPP_F17, NONE),
+/* EMMC_DATA6 */	PAD_NC(GPP_F18, NONE),
+/* EMMC_DATA7 */	PAD_NC(GPP_F19, NONE),
+/* EMMC_RCLK */		PAD_NC(GPP_F20, NONE),
+/* EMMC_CLK */		PAD_NC(GPP_F21, NONE),
+/* EMMC_RESET# */	PAD_NC(GPP_F22, NONE),
+/* A4WP_PRESENT */	PAD_NC(GPP_F23, NONE),
+
+/* SD_CMD */		PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */
+/* SD_DATA0 */		PAD_NC(GPP_G1, NONE),
+/* SD_DATA1 */		PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */
+/* SD_DATA2 */		PAD_NC(GPP_G3, NONE), /* T383 */
+/* SD_DATA3 */		PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */
+/* SD_CD# */		PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */
+/* SD_CLK */		PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */
+/* SD_WP */		PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */
+
+/* I2S2_SCLK */		PAD_NC(GPP_H0, NONE),
+/* I2S2_SFRM */		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */
+/* I2S2_TXD */		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */
+/* I2S2_RXD */		PAD_NC(GPP_H3, NONE),
+/* I2C2_SDA */		PAD_NC(GPP_H4, NONE),
+/* I2C2_SCL */		PAD_NC(GPP_H5, NONE),
+/* I2C3_SDA */		PAD_NC(GPP_H6, NONE),
+/* I2C3_SCL */		PAD_NC(GPP_H7, NONE),
+/* I2C4_SDA */		PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
+/* I2C4_SCL */		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
+/* I2C5_SDA */		PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* ISH_I2C2_SDA */
+/* I2C5_SCL */		PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* ISH_I2C2_SCL */
+/* M2_SKT2_CFG0 */	PAD_NC(GPP_H12, NONE),
+/* M2_SKT2_CFG1 */	PAD_NC(GPP_H13, NONE),
+/* M2_SKT2_CFG2 */	PAD_NC(GPP_H14, NONE),
+/* M2_SKT2_CFG3 */	PAD_NC(GPP_H15, NONE),
+/* DDPF_CTRLCLK */	PAD_NC(GPP_H16, NONE),
+/* DPPF_CTRLDATA */	PAD_NC(GPP_H17, NONE),
+/* CPU_C10_GATE# */	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */
+/* TIMESYNC0 */		PAD_NC(GPP_H19, NONE),
+/* IMGCLKOUT1 */	PAD_NC(GPP_H20, NONE),
+/* GPP_H21 */		PAD_NC(GPP_H21, NONE),
+/* GPP_H22 */		PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */
+/* GPP_H23 */		PAD_NC(GPP_H23, NONE),
+
+/* BATLOW# */		PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */
+/* ACPRESENT */		PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */
+/* LAN_WAKE# */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */
+/* PWRBTN# */		PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */
+/* SLP_S3# */		PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */
+/* SLP_S4# */		PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */
+/* SLP_A# */		PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */
+/* GPD7 */		PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */
+/* SUSCLK */		PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */
+/* SLP_WLAN# */		PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */
+/* SLP_S5# */		PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */
+/* LANPHYC */		PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+/* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
+/* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
+/* I2C4_SDA */		PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
+/* I2C4_SCL */		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
+/* DMIC_DATA1 */	PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
+				 EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
+/* CPU_GP0 */		PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
+/* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
+/* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h
new file mode 100644
index 0000000000..f7e0403e59
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Flash Write Protect */
+#define GPIO_PCH_WP		GPP_E15
+
+/* Recovery mode */
+#define GPIO_REC_MODE		GPP_E8
+
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+struct cros_gpio;
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+#endif