arch/x86: Use the stage argument to implement cbmem_top

Currently all stages that need cbmem need an implementation of a
cbmem_top function.  On FSP and AGESA platforms this proves to be
painful and a pointer to the top of lower memory if often passed via
lower memory (e.g. EBDA) or via a PCI scratchpad register.

The problem with writing to lower memory is that also need to be
written on S3 as one cannot assume it to be still there. Writing
things on S3 is always a fragile thing to do.

A very generic solution is to pass cbmem_top via the program argument.
It should be possible to implement this solution on every
architecture.

Instead trying to figure out which files can be removed from stages
and which cbmem_top implementations need with preprocessor, rename all
cbmem_top implementation to cbmem_top_romstage.

TESTED on qemu-x86.

Change-Id: I6d5a366d6f1bc76f26d459628237e6b2c8ae03ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

9 files changed, 18 insertions, 21 deletions

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 502e7747f4..8ce5977fdb 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -16,6 +16,7 @@ config ARCH_X86
 	default n
 	select PCI
 	select RELOCATABLE_MODULES
+	select RAMSTAGE_CBMEM_TOP_ARG
 
 # stage selectors for x86
 
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8d001745db..447fd57a11 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -259,7 +259,6 @@ postcar-generic-ccopts += -D__POSTCAR__
 postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
 postcar-y += gdt_init.S
 postcar-y += cbfs_and_run.c
-postcar-y += cbmem.c
 postcar-$(CONFIG_EARLY_EBDA_INIT) += ebda.c
 postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
@@ -299,7 +298,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
 ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c
 ramstage-y += c_start.S
-ramstage-y += cbmem.c
 ramstage-y += cpu.c
 ramstage-y += ebda.c
 ramstage-y += exception.c
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 43d78020e1..bd99c21c91 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -60,6 +60,14 @@ _start:
 
 	cld
 
+#ifdef	__x86_64__
+	mov	%rdi, _cbmem_top_ptr
+#else
+	/* The return argument is at 0(%esp), the calling argument at 4(%esp) */
+	movl	4(%esp), %eax
+	movl	%eax, _cbmem_top_ptr
+#endif
+
 	/** poison the stack. Code should not count on the
 	 * stack being full of zeros. This stack poisoning
 	 * recently uncovered a bug in the broadcast SIPI
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index f7c58a47ce..fc85bc617f 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -18,19 +18,8 @@
 
 void *cbmem_top_chipset(void)
 {
-	static void *cbmem_top_backup;
-	void *top_backup;
-
-	if (ENV_RAMSTAGE && cbmem_top_backup != NULL)
-		return cbmem_top_backup;
-
 	/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
-	top_backup = (void *)restore_top_of_low_cacheable();
-
-	if (ENV_RAMSTAGE)
-		cbmem_top_backup = top_backup;
-
-	return top_backup;
+	return (void *)restore_top_of_low_cacheable();
 }
 
 #endif /* CBMEM_TOP_BACKUP */
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index 679e335eb3..8c2878481b 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -31,6 +31,14 @@ _start:
 	/* Migrate GDT to this text segment */
 	call	gdt_init
 
+#ifdef	__x86_64__
+	mov	%rdi, _cbmem_top_ptr
+#else
+	/* The return argument is at 0(%esp), the calling argument at 4(%esp) */
+	movl	4(%esp), %eax
+	movl	%eax, _cbmem_top_ptr
+#endif
+
 	/* chipset_teardown_car() is expected to disable cache-as-ram. */
 	call	chipset_teardown_car
 
diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc
index 4eda3d1049..9b68e13b9b 100644
--- a/src/northbridge/intel/e7505/Makefile.inc
+++ b/src/northbridge/intel/e7505/Makefile.inc
@@ -6,5 +6,4 @@ ramstage-y += memmap.c
 romstage-y += raminit.c
 romstage-y += memmap.c
 
-postcar-y += memmap.c
 endif
diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc
index a167c2369e..f02e3c4aec 100644
--- a/src/northbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc
@@ -18,7 +18,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y)
 
 subdirs-y += fsp
 ramstage-y += northbridge.c
-ramstage-y += memmap.c
 
 ramstage-y += acpi.c
 ramstage-y += port_access.c
diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc
index 2c503c63c1..355d9b2524 100644
--- a/src/northbridge/intel/i440bx/Makefile.inc
+++ b/src/northbridge/intel/i440bx/Makefile.inc
@@ -17,12 +17,9 @@
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y)
 
 ramstage-y += northbridge.c
-ramstage-y += memmap.c
 
 romstage-y += raminit.c
 romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c
 romstage-y += memmap.c
 
-postcar-y += memmap.c
-
 endif
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index cff089149d..3a58cc9235 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -41,7 +41,6 @@ romstage-y += reset.c
 
 postcar-y += fsp_params.c
 postcar-y += i2c.c
-postcar-y += memmap.c
 postcar-y += reg_access.c
 postcar-y += tsc_freq.c
 postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
@@ -53,7 +52,6 @@ ramstage-y += fsp_params.c
 ramstage-y += gpio_i2c.c
 ramstage-y += i2c.c
 ramstage-y += lpc.c
-ramstage-y += memmap.c
 ramstage-y += northcluster.c
 ramstage-y += reg_access.c
 ramstage-y += reset.c