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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-15 05:58:42 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-02-16 09:28:42 +0000
commit4de1a31cb04f0363b6d257d9de392cdfe8d5644c (patch)
tree80a674e5d82d33c5e133d31676ab48bad409798e /3rdparty/intel-sec-tools
parentcdd2f63947549e9b478f26942daf400cf4f246e6 (diff)
ACPI: Add acpi_reset_gnvs_for_wake()
With chipset_power_state filled in romstage CBMEM hooks and GNVS allocated early in ramstage, GNVS wake source is now also filled for normal boot path. Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to '3rdparty/intel-sec-tools')
0 files changed, 0 insertions, 0 deletions