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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-06-16 09:56:26 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-18 04:40:38 +0000 |
| commit | c57d303f9cf18574370878392986224b57595818 (patch) | |
| tree | 419e210a911036dbc636121500257968750b7b2c /3rdparty/intel-microcode | |
| parent | 0faba3cf237df532dce8f61ca6a765c335093bbf (diff) | |
soc/intel/car/cache_as_ram.S: Fix typo in comment
Change-Id: Ia91dbda44f60388324cf58dbccdbd2172dbff21d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55561
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to '3rdparty/intel-microcode')
0 files changed, 0 insertions, 0 deletions