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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-05-05 13:21:01 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2022-08-24 17:18:24 +0000 |
| commit | 9b0f169d2503dc044500e2790b987d766928782a (patch) | |
| tree | 7d38e31cdba9e19389adffc0a7580f040e566ee8 /3rdparty/intel-microcode | |
| parent | b6c32d7fe4ea98ba8b3a10cb5ce46448801855b8 (diff) | |
soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU
PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init.
Implementation based on public Slimbootloader's
"Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib".
TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded.
PCIe x16 Gen3 GPU card started working in the PCIE 5.0 slot.
[DEBUG] HECI: Sending Get IP firmware command
[DEBUG] HECI: Get IP firmware success. Response:
[DEBUG] Payload size = 0x6944
[DEBUG] Hash type used for signing payload = 0x3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to '3rdparty/intel-microcode')
0 files changed, 0 insertions, 0 deletions