sb/intel/common/spi: Fix I/O alignment

On ICH9 the SPI control register is not naturally aligned
and a word write might be split into smaller naturally aligned
I/O transactions.

As the first byte starts a new SPI transfer, replace the existing
word write with two byte writes and write the second byte first.

This is required for platforms that do not support unaligned
word I/O instructions and would start a SPI transfer while the
second byte hasn't reached the control register yet.

TEST: Virtual SPI controller on qemu 8.0 doesn't start a transfer
      early.

Change-Id: Id05b1a080911b71b94ef781c6e26d98165f02f67
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

0 files changed, 0 insertions, 0 deletions