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author | Jeremy Soller <jeremy@system76.com> | 2022-07-26 08:18:38 -0600 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-16 16:17:36 +0000 |
commit | c5d0761dea84b28cd5993b8775a4559974cc8c04 (patch) | |
tree | cf4154e0dfb7c4baf7bff4ca80600ec87340a6e8 /.gitignore | |
parent | 9601b1e273accfbff816cd6e7627862166cfb472 (diff) |
soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID
The Q0 stepping has a different ID than P1.
Reference: CML EDS Volume 1 (Intel doc #606599)
Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to '.gitignore')
0 files changed, 0 insertions, 0 deletions