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authorTan, Lean Sheng <lean.sheng.tan@intel.com>2021-05-24 23:15:43 -0700
committerPatrick Georgi <pgeorgi@google.com>2021-05-30 20:15:42 +0000
commit33f8fc698ca07a1fd38342e5d84f873896d6cc48 (patch)
tree652f2764a6b0bf8d2aec00648c79e06fa02c0003 /.editorconfig
parentf303b4ffd92caf479153245a720c79eca5edb4ba (diff)
soc/intel/elkhartlake: Update FSP-M UPD related configs
Upload the FSP-M UPD configs. This CL also updated the chip.h and devicetree.cb with the relevant variables and configs. This CL also updated the GPIO related settings (PMC & SD card) in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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