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authorElyes HAOUAS <ehaouas@noos.fr>2016-06-26 17:46:21 +0200
committerPatrick Georgi <pgeorgi@google.com>2016-07-12 15:17:31 +0200
commit89186b2eb8167b56bf76d9cc03587d678b9bc661 (patch)
tree8ff8e20b9e71eb37799e34cdb39761fb0b2e3011 /.clang-format
parent74bb41275326cd34046454ab5a06bd7a17d5f887 (diff)
SPD: Add CAS latency 2
CAS latency = 2 support added for DDR2. Change-Id: I08d72a61c27ff0eab19e500a2f547a5e946de2f0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15439 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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