diff options
| author | Keith Hui <buurin@gmail.com> | 2024-04-13 16:04:14 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-16 12:01:09 +0000 |
| commit | ab4de83f4330b76b3026f9097eb801eeb1cdc5b4 (patch) | |
| tree | 81800fc587ece772eaac779bd9124ea79990f40c | |
| parent | 940cbed8d39caca24655ba42ed5d71792041ab64 (diff) | |
sb/intel/ibexpeak: Sever bd82x6x source dependency
It shares southbridge devicetree definition with bd82x6x, causing
changes made there to break builds for boards with this PCH. Give
ibexpeak its own copy.
TEST=abuild tested with lenovo/t410, lenovo/x201, packardbell/ms2290. Timeless binary did not change for all.
Change-Id: I08229ca658bd9c360b6be6137d882d319041b730
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81889
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/ibexpeak/chip.h | 78 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 4 |
2 files changed, 77 insertions, 5 deletions
diff --git a/src/southbridge/intel/ibexpeak/chip.h b/src/southbridge/intel/ibexpeak/chip.h index cf79703a92..aba27ccca8 100644 --- a/src/southbridge/intel/ibexpeak/chip.h +++ b/src/southbridge/intel/ibexpeak/chip.h @@ -3,8 +3,80 @@ #ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H #define SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H -#define southbridge_intel_bd82x6x_config southbridge_intel_ibexpeak_config +#include <southbridge/intel/common/spi.h> +#include <types.h> +#include "pch.h" -#include "../bd82x6x/chip.h" +struct southbridge_intel_ibexpeak_config { + /** + * GPI Routing configuration + * + * Only the lower two bits have a meaning: + * 00: No effect + * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + * 10: SCI (if corresponding GPIO_EN bit is also set) + * 11: reserved + */ + uint8_t gpi0_routing; + uint8_t gpi1_routing; + uint8_t gpi2_routing; + uint8_t gpi3_routing; + uint8_t gpi4_routing; + uint8_t gpi5_routing; + uint8_t gpi6_routing; + uint8_t gpi7_routing; + uint8_t gpi8_routing; + uint8_t gpi9_routing; + uint8_t gpi10_routing; + uint8_t gpi11_routing; + uint8_t gpi12_routing; + uint8_t gpi13_routing; + uint8_t gpi14_routing; + uint8_t gpi15_routing; -#endif + uint32_t gpe0_en; + uint16_t alt_gp_smi_en; + + /* IDE configuration */ + uint8_t sata_port_map; + uint32_t sata_port0_gen3_tx; + uint32_t sata_port1_gen3_tx; + + /** + * SATA Interface Speed Support Configuration + * + * Only the lower two bits have a meaning: + * 00 - No effect (leave as chip default) + * 01 - 1.5 Gb/s maximum speed + * 10 - 3.0 Gb/s maximum speed + * 11 - 6.0 Gb/s maximum speed + */ + uint8_t sata_interface_speed_support; + + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable linear PCIe Root Port function numbers starting at zero */ + bool pcie_port_coalesce; + + /* Override PCIe ASPM */ + uint8_t pcie_aspm[8]; + + int docking_supported; + + bool pcie_hotplug_map[8]; + + /* These USB3 fields, copied from bd82x6x, don't apply here, + * as Ibex Peak doesn't have USB3. */ + uint32_t xhci_switchable_ports; + uint32_t superspeed_capable_ports; + uint32_t xhci_overcurrent_mapping; + + uint32_t spi_uvscc; + uint32_t spi_lvscc; + struct intel_swseq_spi_config spi; +}; + +#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H */ diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index c447746eea..97247612a8 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H -#define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H +#ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_PCH_H +#define SOUTHBRIDGE_INTEL_IBEXPEAK_PCH_H #include <acpi/acpi.h> #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ |